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  Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed therebyUSPTO Application #: 20060019467Title: Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby Abstract: Methods of forming integrated circuit chips include forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon and filling the criss-crossing grooves with an electrically insulating layer. The electrically insulating layer is then patterned to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves. The first and second through-holes are then filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the criss-crossing grooves. (end of abstract) Agent: Myers Bigel Sibley & Sajovec - Raleigh, NC, US Inventors: In-Young Lee, Sung-Min Sim, Dong-Hyeon Jang, Hyun-Soo Chung, Young-Hee Song, Myeong-Soon Park USPTO Applicaton #: 20060019467 - Class: 438462000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Semiconductor Substrate Dicing, Having Specified Scribe Region Structure (e.g., Alignment Mark, Plural Grooves, Etc.) The Patent Description & Claims data below is from USPTO Patent Application 20060019467. Brief Patent Description - Full Patent Description - Patent Application Claims
REFERENCE TO PRIORITY APPLICATION [0001] This application claims priority to Korean Application Serial No. 2004-58689, filed Jul. 23, 2004, the disclosure of which is hereby incorporated herein by reference. FIELD OF THE INVENTION [0002] The present invention relates to methods of fabricating integrated circuit chips and, more particularly, to methods of fabricating integrated circuit chips suitable for multi-chip packaging. BACKGROUND OF THE INVENTION [0003] Multi-chip package (MCP) technologies typically include methods of fabricating integrated circuit chips that may be combined side-by-side or stacked together within a single integrated circuit package or module. The use of MCP technologies can significantly increase the integration density of integrated circuits, including those that are used in hand-held and other small devices (e.g., cellular phones). An example of an MCP technology that uses wiring plugs within penetrant apertures that extent through an integrated circuit chip is disclosed in U.S. Pat. No. 6,429,096 to Yanagida. These wiring plugs support the electrical interconnection of a plurality of chips that can be stacked vertically within a single integrated circuit package. Another example of an MCP technology that uses through-holes is disclosed in U.S. Pat. No. 6,566,232 to Hara et al. [0004] Other packaging technologies that seek to increase the integration densities of integrated circuit chips on a substrate (e.g., printed circuit board (PCB)) include chip scale packaging (CSP) technologies. These CSP technologies seek to increase integration levels using packages that have very small form factors and are nearly the same size as the integrated circuit chip(s) they enclose. One commonly accepted requirement of a CSP package requires that it have a lateral footprint that is no greater than about 1.2 times the size of the semiconductor chip it encloses. An example of a CSP packaging technology is disclosed in U.S. Pat. No. 6,774,475 to Blackshear et al. One type of CSP technology includes wafer-level chip-scale packaging (WLCSP), which enables an integrated circuit chip to be mounted face-down to a printed circuit board (PCB), with the chip's pads connected to the board's pads through individual solder balls without needing any underfill material. This technology differ from other ball-grid array (BGA) technologies because there is typically no bond wires or interposer connections. The principle advantage of WLCSP is that the IC-to-PC board inductance is minimized and the secondary advantages are the reduction in package size and manufacturing cycle time and the enhanced thermal conduction characteristics. Another type of CSP technology, which describes initially forming partial through-holes in a semiconductor substrate and then removing an underside surface of the substrate to expose the through-holes, is disclosed in Korean Laid Open Patent Application No. 2003-0023040. [0005] FIG. 1 illustrates a cross-sectional view of a vertical stack 20 of first and second integrated circuit chips 10a and 10b that are electrically connected together. This vertical stack 20 has some similarities to the vertical stack of chips illustrated at FIG. 12 of the aforementioned Korean Laid Open Patent Application No. 2003-0023040. The first chip 10a is illustrated as including a first semiconductor substrate 12a having a first through-hole 17a therein. The first through-hole 17a extends from an upper surface of the substrate 12a to a lower surface of the substrate 12a. A first passivation layer 13a is provided on the upper surface of the substrate 12a. This first passivation layer 13a has an opening therein that exposes a first chip pad 11a. A first insulating layer 18a is also provided. This first insulating layer 18a extends on the first passivation layer 13a and directly on sidewalls of the first through-hole 17a. A first metal layer 21a is provided directly on the first chip pad 11a and forms an electrical connection therewith. As illustrated, this first metal layer 21a also extends on the first insulating layer 18a and into the first through-hole 17a. The first through-hole 17a is filled with a first electrode metal layer 22a, which is electrically coupled to the first chip pad 11a by the first metal layer 21a. [0006] Similarly, the second chip 10b is illustrated as including a second semiconductor substrate 12b having a second through-hole 17b therein. The second through-hole 17b extends from an upper surface of the substrate 12b to a lower surface of the substrate 12b. A second passivation layer 13b is provided on the upper surface of the substrate 12b. This second passivation layer 13b has an opening therein that exposes a second chip pad 11b. A second insulating layer 18b is also provided. This second insulating layer 18b extends on the second passivation layer 13b and directly on sidewalls of the second through-hole 17b. A second metal layer 21b is provided directly on the second chip pad 11b. This second metal layer 21b also extends on the second insulating layer 18b and into the second through-hole 17b. The second through-hole 17b is filled by a second electrode metal layer 22b, which is electrically coupled to the second chip pad 11b by the second metal layer 21b. [0007] An electrical interconnection is provided between the first and second integrated circuit chips 10a and 10b and the first and second chip pads 11a and 11b. This electrical interconnection is provided by a first metal bump 24a (e.g., solder ball), which electrically connects the first electrode metal layer 22a to the second electrode metal layer 22b. A second metal bump 24b is also provided to electrically connect the second electrode metal layer 22b to an underlying chip, package or printed circuit board (not shown). [0008] As will be understood by those skilled in the art, the first and second integrated circuit chips 10a and 10b may be formed from a common semiconductor wafer (not shown) containing integrated circuits therein and a plurality of chip pads thereon, which are partially covered by a passivation layer (shown as 13a and 13b in FIG. 1). The first and second through-holes 17a and 17b may be formed in the semiconductor wafer using a laser drilling technique. After formation of the through-holes, an insulating layer (shown as 18a and 18b in FIG. 1) is formed on the passivation layer and along sidewalls of the through-holes. This insulating layer may then be patterned to expose the chip pads. A metal layer-(shown as 21a and 21b in FIG. 1) and an electrode metal layer (shown as 22a and 22b in FIG. 1) are then deposited in sequence on the insulating layer. The electrode metal layer is deposited to a thickness sufficient to fill the through-holes. Following these steps, the semiconductor wafer may be thinned by removing a portion of a bottom surface of the semiconductor wafer. This thinning operation may include conventional grinding, polishing and wet etching techniques that result in an exposure of the electrode metal layer within the through-holes. [0009] Unfortunately, the conventional fabrication step of laser drilling to form through-holes in a semiconductor wafer is a relatively lengthy process step that may require each hole to be formed one-at-a-time in sequence. Moreover, the drilling of holes may damage the semiconductor wafer and result in through-holes with tapered sidewall profiles. The formation of tapered sidewall profiles may lead to the formation of electrode metal layers that are susceptible to defects (e.g., electrical disconnection). Thus, notwithstanding these conventional techniques for forming integrated circuit chips that may be stacked together to provide high levels of integration, there continues to be a need for improved methods of forming through-holes in semiconductor wafers and chips. SUMMARY OF THE INVENTION [0010] Semiconductor chips according to embodiments of the present invention use outer edge insulating layers with through-holes therein that provide reliable interconnection vias when the chips are used in stacked multi-chip packaging applications. In some of these embodiments, a semiconductor substrate is provided having upper and lower faces thereon that extend to an outer edge thereof. At least a first contact pad is provided on a portion of the upper face extending adjacent the outer edge. An electrically insulating region is provided on the outer edge of the semiconductor substrate. This electrically insulating region, which may surround an entire periphery of the semiconductor substrate, includes at least one through-hole that extends vertically through an entire thickness of the electrically insulating region and has a longitudinal axis that is substantially parallel to the outer edge of the semiconductor substrate. A connection electrode is also provided. This connection electrode extends through the through-hole and is electrically connected to the first contact pad. The electrically insulating layer may have a lower surface that is coplanar with the lower face of the semiconductor substrate and an upper surface that is above the upper face of the semiconductor substrate, which results in a length of the through-hole being greater than a thickness of the semiconductor substrate. In particular, the electrically insulating layer may wrap around the outer edge and extend onto a passivation layer covering the semiconductor substrate. [0011] Additional embodiments of the invention include a semiconductor chip having a peripheral edge defined by an electrically insulating region having interconnect through-holes therein. The semiconductor chip includes a semiconductor substrate having upper and lower faces thereon that extend to an outer edge thereof. An electrically insulating region is provided on the outer edge of the semiconductor substrate. The electrically insulating region has a through-hole therein that is filled within a connection electrode. A solder bump is also provided. The solder bump is electrically connected to a portion of the connection electrode extending adjacent a bottom of the through-hole. [0012] Still further embodiments of the invention include methods of fabricating a plurality of integrated circuit chips from a semiconductor wafer. These methods include forming a plurality of crisscrossing grooves in a semiconductor wafer having a plurality of contact pads thereon. The criss-crossing grooves are then filled with an electrically insulating layer. The electrically insulating layer is patterned to define at least first and second through-holes therein, which extend into a first one of the criss-crossing groves. The first and second through-holes are filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips. This dicing step may be performed by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the crisscrossing grooves. [0013] In additional embodiments of the invention, the dicing step is preceded by the step of removing an underside of the semiconductor wafer to thereby expose the first and second through-chip connection electrodes and the electrically insulating layer. The step of filling the first and second through-holes may also include depositing a base metal layer that extends on the electrically insulating layer and lines the first and second through-holes and then electroplating the first and second through-chip connection electrodes into the first and second through-holes using the base metal layer as an electroplating electrode. The base metal layer may then be etched back using the first and second through-chip connection electrodes as an etching mask. BRIEF DESCRIPTION OF THE DRAWINGS [0014] FIG. 1 is a cross-sectional view of a stack of integrated circuit chips that is compatible with chip scale packaging technologies, according to the prior art. [0015] FIG. 2 is a plan view of a semiconductor wafer that may be processed in accordance with the methods of FIGS. 3-14 herein. [0016] FIGS. 3-14 are cross-sectional views of intermediate structures that illustrate methods of forming integrated circuit chips according to embodiments of the present invention. [0017] FIG. 15 is a cross-sectional view of a stack of integrated circuit chips formed in accordance with the methods of FIGS. 3-14. DESCRIPTION OF PREFERRED EMBODIMENTS [0018] The present invention now will be described more fully herein with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity of description. It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like elements throughout. Continue reading... Full patent description for Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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