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Methods for patterning dielectric material, and methods for aligning semiconductor fabrication molds and semiconductor substratesRelated Patent Categories: Semiconductor Device Manufacturing: Process, Chemical EtchingMethods for patterning dielectric material, and methods for aligning semiconductor fabrication molds and semiconductor substrates description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060183331, Methods for patterning dielectric material, and methods for aligning semiconductor fabrication molds and semiconductor substrates. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED PATENT DATA [0001] This patent is a divisional of U.S. patent application Ser. No. 10/931,607, filed Aug. 31, 2004, entitled "Semiconductor Processing Methods", which is a continuation of U.S. patent application Ser. No. 10/461,811, filed Jun. 12, 2003, entitled "Methods of Forming Patterns for Semiconductor Constructions", which is a divisional of U.S. patent application Ser. No. 10/099,840, filed Mar. 12, 2002, entitled "Methods of Forming Patterns and Molds for Semiconductor Constructions", now U.S. Pat. No. 6,716,542 B2; the entirety of all of which are incorporated by reference herein. TECHNICAL FIELD [0002] The invention pertains to methods of forming patterns for semiconductor constructions, and in particular applications pertains methods of utilizing contact lithography for forming patterns. The invention also encompasses molds configured to pattern masses associated with semiconductor constructions. BACKGROUND OF THE INVENTION [0003] A prior art semiconductor construction 10 is described with reference to FIG. 1. Construction 10 comprises a substrate 12 having a plurality of conductive pads 14, 16 and 18 supported thereover. Pads 14, 16 and 18 can comprise various conductive materials, including, for example, copper and/or aluminum. Substrate 12 can comprise, for example, a monocrystalline silicon wafer having a plurality of circuit constructions (not shown), such as memory or logic constructions, supported thereon. To aid in interpretation of the claims that follow, the terms "semiconductive substrate" and "semiconductor substrate" are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. [0004] Pads 14, 16 and 18 correspond to electrical interconnects which join the various circuitry (not shown) associated with substrate 12 to electrical components (not shown) external of substrate 12. Substrate 12 can be considered an integrated circuit component, and pads 14, 16 and 18 can correspond to, for example, bonding pads or so-called Level III wiring. [0005] Pads 14, 16 and 18 can be considered to comprise or define electrical nodes. Presently, efforts are underway to redistribute electrical connections from bonding pads to other regions of semiconductor circuitry. The redistribution of the electrical connections can simplify electrical connection of integrated circuitry associated with a semiconductor construction to other circuitry which is external of the semiconductor construction. FIG. 1 illustrates a plurality of redistribution layers 20, 22, and 24 which are electrically connected with bonding pads 14, 16 and 18 respectively. [0006] A dielectric material 26 separates redistribution layers 20, 22 and 24 from one another. Dielectric material 26 can comprise, for example, a so-called low-k dielectric material, with the term "low-k" referring to a dielectric material having a dielectric constant below 3.5. An exemplary low-k dielectric material is CYCLOTENE.TM., which is available from the Dow Chemical Company.TM.. Redistribution layers 20, 22 and 24 can be referred to as Level IV wiring, and can comprise, for example, copper and/or aluminum. [0007] An insulative material 28 is formed over redistribution layers 20, 22 and 24; and openings are formed through insulative material 28 to redistribution layers 20, 22, and 24. Subsequently, conductive materials 30 and 32 are formed within the openings. Conductive materials 30 and 32 can comprise, for example, a copper seed layer and sputter-deposited copper, respectively. After formation of layers 30 and 32, a pair of under bump metal layers 34 and 36 are provided, and subsequently solder bumps 38 are formed over the under bump layers and in electrical connection with redistribution layers 20, 22 and 24 through conductive materials 30 and 32. Under bump layers 34 and 36 can comprise, for example, nickel and gold, respectively; and solder bumps 38 can comprise, for example, tin-based solder. In further processing (not shown) solder bumps 38 can be connected with conductive materials external of construction 10 to electrically interconnect integrated circuitry associated with structure 10 to such external components. [0008] Numerous difficulties are encountered in forming appropriate openings in insulative material 26 for redistribution layers 20, 22 and 24; and further problems are encountered in forming openings in insulative material 28 for conductive materials 30 and 32. It would be desirable to develop methodology which alleviates or eliminates such problems and difficulties. SUMMARY OF THE INVENTION [0009] In one aspect, the invention encompasses methods of forming patterns in low-k dielectric materials by contact lithography. In a particular application a mold having a first pattern is pressed into a low-k dielectric material to form a second pattern within the material. The second pattern is substantially complementary to the first pattern. The mold is then removed from the low-k dielectric material. [0010] In another aspect, the invention encompasses a method of forming a mold. A template is provided which has a complement of a desired mold pattern thereover. The template is approximately the size of a semiconductor wafer and the desired mold pattern is a pattern utilized for contact lithography during semiconductor processing. A sheet having holes extending therethrough is provided. A mold material precursor is provided between the sheet and the template, and is pressed between the sheet and template. The mold material precursor is cured during the pressing to convert the precursor to a mold material having the desired mold pattern. The mold material penetrates through the openings in the sheet and is joined with the sheet to define a mold comprising the mold material and the sheet. The mold is subsequently removed from the template. [0011] In another aspect, the invention encompasses a mold configured to pattern a mass over a semiconductor substrate during contact lithography of the mass. The mold includes a substantially rigid sheet having holes extending therethrough, and a patterned material joined to the sheet. The patterned material extends through the holes in the sheet, and has a pattern therein which is a reverse image of a pattern which is to be formed in the mass during contact lithography. BRIEF DESCRIPTION OF THE DRAWINGS [0012] Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0013] FIG. 1 is a diagrammatic, cross-sectional, fragmentary view of a prior art semiconductor wafer construction. [0014] FIG. 2 is a diagrammatic, fragmentary, cross-sectional view of a semiconductor wafer construction at a preliminary processing step of a method of the present invention. [0015] FIG. 3 is a view of the FIG. 2 wafer construction illustrated juxtaposed with a mold, in accordance with a processing step subsequent to that of FIG. 2. [0016] FIG. 4 is a view of the FIG. 2 wafer construction shown at a processing step subsequent to that of FIG. 2, and shown with the FIG. 3 mold pressed into the FIG. 2 wafer construction. [0017] FIG. 5 is a view of the FIG. 2 wafer construction shown at a processing step subsequent to that of FIG. 4. [0018] FIG. 6 is a view of the FIG. 2 wafer construction shown at a processing step subsequent to that of FIG. 5. [0019] FIG. 7 is a view of the FIG. 2 wafer construction shown at a processing step subsequent to that of FIG. 6. Continue reading about Methods for patterning dielectric material, and methods for aligning semiconductor fabrication molds and semiconductor substrates... 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