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Methods for forming material layers with substantially planar surfaces on semiconductor device structuresRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor SubstrateMethods for forming material layers with substantially planar surfaces on semiconductor device structures description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070004221, Methods for forming material layers with substantially planar surfaces on semiconductor device structures. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of application Ser. No. 09/542,783, filed Apr. 4, 2000, pending. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to methods for filling containers, trenches, or other recesses of semiconductor device structures during fabrication thereof. Particularly, the present invention relates to the use of spin coating techniques to fill containers, trenches, and other recesses of semiconductor device structures. As a specific example, the present invention relates to a method for masking hemispherical grain (HSG) silicon-lined containers of a stacked capacitor structure to facilitate removal of HSG silicon from the surface of a semiconductor device structure including the stacked capacitor structure. [0004] 2. Background of Related Art [0005] Conventionally, spin-on processes have been used to apply substantially planar layers of material to the surfaces of semiconductor device structures being fabricated upon a wafer of semiconductor material (e.g., a silicon, gallium arsenide, or indium phosphide wafer) or other semiconductor substrate (e.g., a silicon on insulator (SOI), silicon on glass (SOG), silicon on ceramic (SOC), silicon on sapphire (SOS), or other similar substrate). Consequently, while the portions of a spun-on layer of material over substantially horizontal structures may be substantially planar, the layer of material may not substantially fill or conform to the numerous, minute recesses formed in the semiconductor device structure. [0006] For example, when it is desirable to mask a container, trench, or other recess of a semiconductor device structure without masking the surface of the semiconductor device structure to which the container, trench, or other recess opens, a mask material is typically applied to the surface of the semiconductor device structure, such as by use of known spin-on processes. As an example, FIG. 1 illustrates the fabrication of a stacked capacitor structure 10 with conductively doped HSG silicon 16-lined containers 14. As it is necessary to remove HSG silicon 16 from a surface 12 of an electrical insulator layer 11 (e.g., borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or borosilicate glass (BSG)) of stacked capacitor structure 10 to prevent electrical shorting between adjacent containers 14, mask material 18' is introduced into containers 14 to facilitate removal of HSG silicon 16 from surface 12. [0007] While conventional spin-on processes will force some of the mask material into containers 14, trenches, or other recesses, these processes typically result in the formation of a relatively thick, but not necessarily planar layer of mask material 18' over surface 12. Due to various factors, including the surface tension of mask material 18' and the centrifugal forces applied to mask material 18' during the spin-on process, mask material 18' tends to migrate out of the small recesses (e.g., containers 14) formed in surface 12. Thus, the thickness of mask material 18' within a container 14, trench, or other recess may not be significantly greater than the thickness of mask material 18' covering surface 12, leaving containers 14 partially unfilled. Once the layer of material has been dispensed onto the semiconductor device structure, it is solidified or cured, such as by known photographic or soft bake processes. [0008] In order to reduce the thickness of the layer of mask material covering the surface of the semiconductor device structure without substantially decreasing the thickness of the layer of mask material within the recesses, chemical-mechanical planarization (CMP) processes, such as chemical-mechanical polishing techniques, are typically employed. The use of CMP processes is, however, somewhat undesirable since such processes are known to create defects in the surface of the semiconductor device structure. CMP processes are also known to leave debris, or contaminants, which may be trapped in defects in the surface of the semiconductor device structure and which may subsequently cause electrical shorting of a fabricated semiconductor device. For example, if CMP processes are used to remove mask material and at least part of a conductively doped HSG silicon layer from an insulator at the surface of a stacked capacitor structure, conductive silicon particles may be trapped in defects in the surface of the insulator and subsequently cause electrical shorting between adjacent containers of the stacked capacitor. These potentially damaging contaminants may remain even when a chemical removal process, such as a wet or dry etch, follows the CMP process. [0009] Alternatively, a photoresist may be used as the mask material. Patterning of the photoresist requires several steps in which equipment must be precisely aligned with features, such as the containers of a stacked capacitor structure, fabricated on the semiconductor substrate. Additional handling of the semiconductor device structure is also required when a photoresist is used to mask containers, trenches, or other recesses formed in a semiconductor device structure, which is somewhat undesirable. [0010] Moreover, when conventional blanket deposition techniques are used to fill the recesses of a semiconductor device structure with a material (e.g., to fill the trenches of a shallow trench isolation structure with an electrical insulator material and to fill dual damascene trenches with a conductive material), the material typically forms a nonplanar layer over the semiconductor device structure. Such material layers typically include valleys located over recesses in the underlying semiconductor device structure and peaks located over other regions of the semiconductor device structure. Chemical-mechanical planarization is an example of a conventional technique for removing such materials from the surface of a semiconductor device structure while leaving these materials within the recesses of the semiconductor device structure. As chemical-mechanical planarization processes typically employ an abrasive pad to mechanically planarize structures, however, the peaks of the material layer may break off in larger than desired pieces and subsequently scratch the surface of the semiconductor device structure, forming defects therein. [0011] The art does not teach a semiconductor device structure that includes a nonchemical-mechanical planarized material layer that substantially fills a container, trench, or other recess formed in the semiconductor device structure and which does not substantially cover the remainder of a surface of the semiconductor device structure or which includes only a relatively thin layer of material over the remainder of the surface. The art also fails to teach a method for forming a material layer with these features. In addition, the art lacks teaching of a method for reducing the likelihood that peaks of a nonplanar layer of material will damage a surface of a semiconductor device structure during subsequent planarization of the layer of material. SUMMARY OF THE INVENTION [0012] The present invention includes semiconductor device structures with substantially planar surfaces. The semiconductor device structures also include containers, trenches, or other recesses that are filled with a material. The material may also cover adjacent surfaces of the semiconductor device structures. If the material covers surfaces of the semiconductor device structures, the thickness of the material covering the surface is less than the depth of the containers, trenches, or other recesses that are substantially filled with material. Preferably, the thicknesses of material covering the surfaces of the semiconductor device structures are less than about half the depth of the containers, trenches, or other recesses. The surfaces of the material or materials that fill the recesses and that may cover the surfaces of the semiconductor device structures have not, however, been chemical-mechanical planarized to achieve the reduced depth of material outside of the recesses. [0013] In one embodiment of the present invention, the semiconductor device structure includes a stacked capacitor structure with a layer of electrically insulative material, or insulator layer, and at least one container recessed or formed in the insulator layer. The insulator layer includes a substantially planar surface, which is referred to herein as the exposed surface of the insulator layer. A layer of electrically conductive material covers the surface of the insulator layer and lines the at least one container. By way of example, the electrically conductive material may be conductively doped hemispherical grain (HSG) silicon. As the stacked capacitor structure would electrically short if the conductive material remained on the surface of the insulator layer between adjacent containers, for the stacked capacitor to function properly, the conductive material must be removed from the surface of the insulator layer prior to completing fabrication of the stacked capacitor but remain within the containers. Thus, this embodiment of the semiconductor device structure includes a substantially planar surface with a nonchemical-mechanical planarized quantity of mask material substantially filling the at least one container. While the mask material may cover regions of the layer of conductive material overlying the surface of the insulator layer, it is preferred that these regions are substantially uncovered by mask material. If mask material does overlie these regions of the layer of conductive material, the thickness of the mask material overlying these regions is less than the depth of the at least one container. Preferably, the thickness of the mask material over these regions of the layer of conductive material is less than about half the depth of the at least one container. [0014] The mask material may be applied to the semiconductor device structure by known processes and is spread across the surface of the stacked capacitor structure so as to substantially fill the at least one container while leaving a thinner, or no, material layer over regions of the layer of conductive material that overlie the surface of the insulator layer. For example, the mask material may be spread across the surface of the stacked capacitor structure by use of spin-on techniques, wherein the mask material is applied at a first speed, the rate of spinning is decreased to a second speed at which the mask material is permitted to at least partially set up, then the rate of spinning is gradually increased, or ramped up, to a third speed at which a desired, reduced thickness of mask material covering the surface may be obtained. The rate at which the stacked capacitor structure is spun may again be decreased to permit the mask material to further set. An edge bead of mask material may then be removed from the stacked capacitor structure and the stacked capacitor structure spun once again to remove solvents from the mask material. [0015] In another embodiment of the semiconductor device structure, a mask is disposed over a shallow trench isolation (STI) structure that includes a semiconductor substrate with a substantially planar surface and shallow trenches recessed, or formed, in the semiconductor substrate. The semiconductor device structure has a substantially planar surface, without requiring chemical-mechanical planarization of the surface of the mask. If material of the mask covers the surface of the semiconductor substrate, the thickness of mask material thereover is significantly less than the depths of the shallow trenches. Preferably, the thickness of mask material covering the surface of the semiconductor substrate is less than about half the depths of the trenches. More preferably, the surface of the semiconductor substrate remains substantially uncovered by the mask material. The present embodiment of the semiconductor substrate may also include conductively doped regions continuous with the surface and located between the trenches formed in the semiconductor substrate. [0016] The shallow trench isolation structure may be formed by known processes. The mask may be formed by applying a quantity of mask material to the shallow trench isolation structure and spreading the mask material over the surface so as to substantially fill each trench thereof. As an example of the manner in which mask material may be spread across the shallow trench isolation structure, the mask material may be spun across the semiconductor substrate at a first speed, the rate of spinning decreased to a second speed to permit the mask material to at least partially set up while remaining in the trenches, then the rate of spinning gradually increased, or ramped up, to a third speed at which a desired, reduced thickness of mask material covering the surface may be obtained. The rate at which the shallow trench isolation structure is spun may again be decreased to permit the mask material to further set. An edge bead of mask material may then be removed from the shallow trench isolation structure and the shallow trench isolation structure spun once again to remove solvents from the mask material. Conductively doped regions of the semiconductor substrate may be formed by exposing the substrate and mask material to a conductivity dopant. The regions of the semiconductor substrate that remain uncovered or that are covered with thinner layers of the mask material (e.g., the surface of the semiconductor substrate) are implanted with the conductivity dopant while regions of the semiconductor substrate that are covered with thicker layers of the mask material (e.g., regions of the semiconductor substrate beneath the trenches) remain substantially undoped. [0017] Another embodiment of a semiconductor device structure according to the present invention includes a surface with one or more recesses formed therein and a layer of a first material substantially filling each recess and at least partially covering the surface. The layer of first material has a nonplanar surface and may include a valley located substantially over each recess in the semiconductor device structure and one or more peaks located substantially over the surface of the semiconductor device structure. A second material disposed over the layer of first material at least partially fills each of the valleys formed in the layer of first material. The second material has a substantially planar surface that is not further planarized following formation thereof. [0018] By way of example, the semiconductor device structure may be a shallow trench isolation structure including a semiconductor substrate with a substantially planar surface and trenches recessed, or formed, in the semiconductor substrate. The trenches are filled with a first, electrically insulative material, which is preferably a low dielectric constant, or "low-k," material, such as a high density plasma (HDP) silicon oxide, or HDP oxide. HDP oxide or another insulative material may be disposed into the trenches by way of known processes, such as chemical vapor deposition (CVD) processes. As the processes that are used to fill the shallow trenches with the first, insulative material are typically blanket deposition processes, the insulative material may also cover the surface of the semiconductor substrate. The surface of a layer of the first, insulative material blanket deposited over a semiconductor substrate with trenches formed therein is nonplanar. [0019] As another example of the deposition of a first material over a semiconductor device structure, each recess of the semiconductor device structure may be a dual damascene type trench substantially filled with a first, conductive material. The first, conductive material may be disposed into each dual damascene trench of the semiconductor device structure by known processes, such as physical vapor deposition (PVD) (e.g., sputtering) or chemical vapor deposition techniques. Since these processes typically form a layer of material that blankets substantially the entire semiconductor device structure, the first, conductive material may also cover the surface of the semiconductor device structure. When blanket deposited over a semiconductor device structure with trenches formed therein, such layers typically have nonplanar surfaces. [0020] The second material is preferably a stress buffer material that facilitates planarization of the layer of insulative material without causing substantial defects in either the insulative material or in the surface of the underlying semiconductor substrate. Exemplary materials that are useful as the stress buffer include resins and polymers that may be applied by way of spin-on techniques. The stress buffer has a substantially planar surface and preferably fills the valleys in the layer of insulative material without substantially covering the peaks thereof. [0021] After the stress buffer material is applied to the semiconductor device structure, it may be spread across the surface of the semiconductor device structure by a spin-on technique that includes spinning the semiconductor device structure at a first speed, decreasing the rate of spinning to a second speed at which the material of the stress buffer within the valleys is permitted to at least partially set, then gradually increasing, or ramping up, the rate of spinning to a third speed at which a desired thickness of stress buffer material covering the surface may be obtained. The rate at which the semiconductor device structure is spun may again be decreased to permit the stress buffer material to further set. An edge bead of stress buffer material may then be removed from the semiconductor device structure and the semiconductor device structure spun once again to remove solvents from the stress buffer material. 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