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Methods for forming alignment marks on semiconductor devicesRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Device Or Circuit Responsive To Nonelectrical Signal, Responsive To Electromagnetic Radiation, Continuous Processing, Using Running Length SubstrateMethods for forming alignment marks on semiconductor devices description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070172977, Methods for forming alignment marks on semiconductor devices. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION [0001] This application is a divisional of U.S. patent application Ser. No. 10/960,660, filed Oct. 7, 2004, and claims priority under 35 U.S.C. .sctn.119 to Korean Patent Application No. 10-2003-0070974, filed on Oct. 13, 2003, in the Korean Intellectual Property Office, the disclosures of which are herein incorporated by reference in their entirety. FIELD OF THE INVENTION [0002] The present invention relates to analysis of semiconductor devices, and more particularly, to semiconductor devices having alignment marks and related methods. BACKGROUND OF THE INVENTION [0003] Semiconductor memory devices generally include arrays of cells that form memory units. Each of the cells can include a transistor pattern having a gate and source/drain regions. To obtain ever higher integration density in the memory devices, gate lengths and intervals between gates are continuing to be reduced. For example, in some memory devices the source/drain regions can have a width of less than several tens of nanometers. [0004] The small size of some transistor patterns may cause them to be difficult to observe with an optical microscope. Consequently, it can be difficult to detect and identify a particular failed cell in a memory device. For example, it may not be feasible to optically count numerous small cells in a memory device in an attempt to determine an address of a failed cell. Moreover, when a cell region has failed because of a doping abnormality, such a failure may be difficult to optically observe because the region may appear optically identical to other normal regions. [0005] One approach to analyzing memory cells or other device features is to expose a vertical profile of a cell that is to be analyzed. For example, it can be desirable to obtain a vertical profile of a failed cell address in a memory device by grinding a side face of the memory device to expose regions of the failed cell address. However, it may not be feasibly to optically identify a failed cell address with the memory device, and then to expose regions of that particular cell address so that they may be further analyzed. [0006] A cell region can be inspected with a scanning microscope (SCM). A SCM can include a capacitance sensor and a probe. The capacitance sensor is electrically connected to the probe for measuring a capacitance between the probe and the cell region. The probe and cell region may, for example, have nanometer feature sizes. The capacitance sensor includes a high-frequency oscillator and an electrical resonator. The capacitance, which can have a very low value, is measured by varying a resonance frequency that is based on the capacitance. For example, a high frequency measured signal can be modulated onto a low frequency signal. A differential value of the capacitance relative to a voltage may be measured using a lock-in amplifier. The SCM can measure carrier concentrations and second dimensional doping profiles of the cell regions. [0007] Accordingly, if a failed cell region can be exposed for analysis by a SCM, the doping profiles measured by the SCM may provide an answer as to why the cell region failed. SUMMARY OF THE INVENTION [0008] According to some embodiments of the present invention, a semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks. [0009] According to further embodiments of the present invention, one of the second alignment marks may be on the device feature. The third alignment marks may be trenches in the semiconductor device. A pair of trench type fourth alignment marks may be directly connected to the first alignment marks and aligned therewith. The first alignment marks may be between the fourth alignment marks and the device feature. [0010] According to still further embodiments of the present invention, a first auxiliary alignment mark may be aligned with the second alignment marks and the device feature along the second direction. One of the second alignment marks may be between the first auxiliary alignment mark and the device feature. The first auxiliary alignment mark may have a variable cross-section width along the first direction. [0011] According to still further embodiments of the present invention, a side face of the semiconductor device is ground in the second direction to substantially simultaneously expose the first alignment marks, the second alignment mark on the device feature, and the third alignment marks. An amount of the side face of the semiconductor device that is to be removed by grinding to expose the first alignment marks, the second alignment mark on the device feature, and the third alignment marks may be estimated based on the cross-section width of the first auxiliary alignment mark along the first direction. A rate of grinding of the side face of the semiconductor device may be reduced based on the cross-section width of the first auxiliary alignment mark along the first direction. A rate of grinding of the side face of the semiconductor device may be reduced based on exposure of a first one of the pair of second alignment marks. A rate of grinding of the side face of the semiconductor device may be reduced based on exposure of the third marks. The grinding of the side face of the semiconductor device may be stopped based on exposure of the second alignment mark on the device feature. [0012] Some other embodiments of the present invention provide a method for exposing at least a portion of a defective device feature on a semiconductor device. A plurality of alignment marks are formed on the semiconductor device. Portions of the semiconductor device are ground away to expose the defective device feature. The rate of grinding is varied based on the alignment marks. BRIEF DESCRIPTION OF THE DRAWINGS [0013] FIG. 1 is a plan view of alignment marks adjacent to a semiconductor device feature in accordance with various embodiment of the present invention; [0014] FIGS. 2 to 6 are cross sectional views that illustrate methods for forming alignment marks adjacent to a semiconductor device feature, and for grinding the semiconductor device to expose a surface of the device feature in accordance with various embodiments of the present invention; and [0015] FIGS. 7A to 7C are sequential plan views of a semiconductor device that has been ground to expose a side surface of a device feature in accordance with various embodiments of the present invention. DETAILED DESCRIPTION [0016] Certain embodiments of the present invention now will be described more fully hereinafter with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. [0017] In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. [0018] Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to, for example, the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted, deposited, and/or etched region illustrated as a rectangle will, typically, have rounded or curved features at its edges. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention. Continue reading about Methods for forming alignment marks on semiconductor devices... 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