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04/24/08 - USPTO Class 438 |  21 views | #20080096313 | Prev - Next | About this Page  438 rss/xml feed  monitor keywords

Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates

USPTO Application #: 20080096313
Title: Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
Abstract: A projection system, a spatial light modulator, and a method for forming a MEMS device is disclosed. The spatial light modulator can have two substrates bonded together with one of the substrates comprising a micromirror array. The two substrates can be bonded at the wafer level after depositing a getter material and/or solid or liquid lubricant on one or both of the wafers. The wafers can be bonded together hermetically if desired, and the pressure between the two substrates can be below atmosphere. (end of abstract)



Agent: Texas Instruments Incorporated - Dallas, TX, US
Inventors: Satayadev R. Patel, Andrew G. Huibers, Steve Chiang, Robert M. Duboc, Thomas J. Grobelny, Hung Nan Chen, Dietrich Dehlinger, Peter W. Richards, Hongqin Shi, Anthony Sun
USPTO Applicaton #: 20080096313 - Class: 438107000 (USPTO)

Related Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor, Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device

Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20080096313, Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates.

Brief Patent Description - Full Patent Description - Patent Application Claims
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[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 10/005,308 to Patel et al. filed Dec. 3, 2001, which claims priority from U.S. provisional application 60/254,043 to Patel et al. filed Dec. 7, 2000 and U.S. provisional application 60/276,222 to Patel et al. filed Mar. 15, 2001, each of the above incorporated herein by reference.

[0002] The present invention is in the field of MEMS, and in particular in the field of methods for making micro electromechanical devices on a wafer. The subject matter of the present invention is related to manufacturing of multiple MEMS devices on a wafer, releasing the MEMS structures by removing a sacrificial material, bonding the wafer to another wafer, singulating the wafer assembly, and packaging each wafer assembly portion with one or more MEMS devices thereon, without damaging the MEMS microstructures thereon. A wide variety of micro-electromechanical devices (MEMS) devices can be made in accordance with the embodiments herein, including accelerometers, DC relay and RF switches, optical cross connects and optical switches, microlenses, reflectors and beam splitters, filters, oscillators and antenna system components, variable capacitors and inductors, switched banks of filters, resonant comb-drives and resonant beams, and micromirror arrays for direct view and projection displays.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] FIGS. 1A to 1E are cross sectional views illustrating one method for forming micromirrors;

[0004] FIG. 2 is a top view of a micromirror showing line 1-1 for taking the cross section for FIGS. 1A to 1E;

[0005] FIGS. 3A to 3E are cross sectional views illustrating the same method as in FIGS. 1A to 1E but taken along a different cross section;

[0006] FIG. 4 is a top view of a mirror showing line 3-3 for taking the cross section for FIGS. 3A to 3E;

[0007] FIG. 5 is an isometric view of the assembly of two substrates, one with micromirrors, the other with circuitry and electrodes;

[0008] FIG. 6 is a cross sectional view of the assembled device in use;

[0009] FIG. 7 is a flow chart of one method of the invention;

[0010] FIG. 8 is a top view of a wafer substrate having multiple die areas;

[0011] FIGS. 9A to 9G are step-by-step views of the assembly of the device;

[0012] FIGS. 10A and 10B are top views of two wafers that will be joined together and then singulated;

[0013] FIGS. 10C and 10D are views of light transmissive substrates (FIG. 10A) for bonding to a wafer (10D);

[0014] FIG. 11A is a cross sectional view taken along line 11-11 of FIG. 10 upon alignment of the two wafers of FIGS. 10A and 10B, but prior to bonding, whereas FIG. 11B is the same cross sectional view after bonding of the two wafers, but prior to singulation;

[0015] FIG. 12 is an isometric view of a singulated wafer assembly die held on a package substrate; and

[0016] FIG. 13 is an illustration of a projection system having a micromirror device therein.

DETAILED DESCRIPTION

Mirror Fabrication:

[0017] Processes for microfabricating a MEMS device such as a movable micromirror and mirror array are disclosed in U.S. Pat. Nos. 5,835,256 and 6,046,840 both to Huibers, the subject matter of each being incorporated herein by reference. A similar process for forming MEMS movable elements (e.g. mirrors) on a wafer substrate (e.g. a light transmissive substrate or a substrate comprising CMOS or other circuitry) is illustrated in FIGS. 1 to 4. By "light transmissive", it is meant that the material will be transmissive to light at least in operation of the device (The material could temporarily have a light blocking layer on it to improve the ability to handle the substrate during manufacture, or a partial light blocking layer for decreasing light scatter during use. Regardless, a portion of the substrate, for visible light applications, is preferably transmissive to visible light during use so that light can pass into the device, be reflected by the mirrors, and pass back out of the device. Of course, not all embodiments will use a light transmissive substrate). By "wafer" it is meant any substrate on which multiple microstructures or microstructure arrays are to be formed and which allows for being divided into dies, each die having one or more microstructures thereon. Though not in every situation, often each die is one device or product to be packaged and sold separately. Forming multiple "products" or dies on a larger substrate or wafer allows for lower and faster manufacturing costs as compared to forming each die separately. Of course the wafers can be any size or shape, though it is preferred that the wafers be the conventional round or substantially round wafers (e.g. 4'', 6'' or 12'' in diameter) so as to allow for manufacture in a standard foundry.

[0018] FIGS. 1A to 1E show a manufacturing process for a micromechanical mirror structure. As can be seen in FIG. 1A, a substrate such as glass (e.g. 1737 F), quartz, Pyrex.TM., sapphire, (or silicon alone or with circuitry thereon) etc. is provided. The cross section of FIGS. 1A-E is taken along line 1-1 of FIG. 2. Because this cross section is taken along the hinge of the movable element, an optional block layer 12 can be provided to block light (incident through the light transmissive substrate during use) from reflecting off of the hinge and potentially causing diffraction and lowering the contrast ratio (if the substrate is transparent).

[0019] As can be seen in FIG. 1B, a sacrificial layer 14, such as amorphous silicon, is deposited. The thickness of the sacrificial layer can be wide ranging depending upon the movable element/mirror size and desired tilt angle, though a thickness of from 500 .ANG. to 50,000 .ANG., preferably around 5000 .ANG. is preferred. Alternatively the sacrificial layer could be a polymer or polyimide (or even polysilicon, silicon nitride, silicon dioxide, etc. depending upon the materials selected to be resistant to the etchant, and the etchant selected). A lithography step followed by a sacrificial layer etch forms holes 16a,b in the sacrificial silicon, which can be any suitable size, though preferably having a diameter of from 0.1 to 1.5 um, more preferably around 0.7+/-0.25 um. The etching is performed down to the glass/quartz substrate or down to the block layer if present. Preferably if the glass/quartz layer is etched, it is in an amount less than 2000 .ANG..

[0020] At this point, as can be seen in FIG. 1C, a first layer 18 is deposited by chemical vapor deposition. Preferably the material is silicon nitride or silicon oxide deposited by LPCVD or PECVD, however polysilicon, silicon carbide or an organic compound could be deposited at this point--or Al, CoSiNx, TiSiNx, TaSiNx and other ternary and higher compounds as set forth in U.S. patent application Ser. No. 09/910,537 filed Jul. 20, 2001, and 60/300,533 filed Jun. 22, 2001 both to Reid and incorporated herein by reference (of course the sacrificial layer and etchant should be adapted to the material used). The thickness of this first layer can vary depending upon the movable element size and desired amount of stiffness of the element, however in one embodiment the layer has a thickness of from 100 to 3200 .ANG., more preferably around 1100 .ANG.. The first layer undergoes lithography and etching so as to form gaps between adjacent movable elements on the order of from 0.1 to 25 um, preferably around 1 to 2 um.

[0021] A second layer 20 (the "hinge" layer) is deposited as can be seen in FIG. 1D. By "hinge layer" it is meant the layer that defines that portion of the device that flexes to allow movement of the device. The hinge layer can be disposed only for defining the hinge, or for defining the hinge and other areas such as the mirror. In any case, the reinforcing material is removed prior to depositing the hinge material. The material for the second (hinge) layer can be the same (e.g. silicon nitride) as the first layer or different (silicon oxide, silicon carbide, polysilicon, or Al, CoSiNx, TiSiNx, TaSiNx or other ternary and higher compounds) and can be deposited by chemical vapor deposition as for the first layer. The thickness of the second/hinge layer can be greater or less than the first, depending upon the stiffness of the movable element, the flexibility of the hinge desired, the material used, etc. In one embodiment the second layer has a thickness of from 50 .ANG. to 2100 .ANG., and preferably around 500 .ANG.. In another embodiment, the first layer is deposited by PECVD and the second layer by LPCVD.

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