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  Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stagesUSPTO Application #: 20070094622Title: Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages Abstract: Operations for generating an integrated circuit netlist include generating a first schematic of an integrated circuit having a plurality of cells therein and generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the pre-layout interconnects. The first and second schematics are then combined at corresponding first and second ports within the first and second schematics, respectively. Operations also include generating an integrated circuit netlist by generating a circuit schematic that defines post-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the post-layout interconnects. This circuit schematic is then combined with the first schematic at corresponding first and second ports therein. These embodiments may also be configured to generate a layout schematic from the first schematic of the integrated circuit and generate parasitic resistances and capacitances of the post-layout interconnects that extend between a plurality of cells in the layout schematic. Operations are then performed to generate parasitic resistances and capacitances of interconnects internal to at least one cell in the layout schematic. (end of abstract) Agent: Myers Bigel Sibley & Sajovec - Raleigh, NC, US Inventors: Jong-bae Lee, Moon-hyun Yoo, Kyo-sun Kim, Jeong-min Choi USPTO Applicaton #: 20070094622 - Class: 716004000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or Evaluating The Patent Description & Claims data below is from USPTO Patent Application 20070094622. Brief Patent Description - Full Patent Description - Patent Application Claims
REFERENCE TO PRIORITY APPLICATION [0001] This application is a divisional of U.S. application Ser. No. 10/629,154, filed Jul. 29, 2003, which claims priority to Korean Application No. 2002-76695, filed on Dec. 4, 2002. The disclosure of U.S. application Ser. No. 10/629,154 is hereby incorporated herein by reference. FIELD OF THE INVENTION [0002] The present invention relates to circuit design units, and more particularly, to devices for generating integrated circuit netlists that support device simulation. BACKGROUND OF THE INVENTION [0003] In general, the design of semiconductor integrated circuits follows a set method. To begin with, a schematic circuit, which is a diagram showing connections between circuit devices, can be designed by a schematic tool. Next, the respective circuit devices included in the schematic circuit can be designed by patterns of such material layers as a conductive layer, a semiconductor layer, and an insulation layer. Then, a layout is designed where the respective patterns are disposed in vertical and horizontal directions, and the respective material layers are repeatedly deposited and patterned based on the layout. Thus, a semiconductor integrated circuit having a desired function can be manufactured. [0004] When a schematic circuit of a semiconductor integrated circuit is drawn by a schematic tool, a netlist extracted from the schematic tool is simulated using a simulation device to inspect the operation of the semiconductor integrated circuit. If the results of the simulation are not satisfactory, the schematic circuit is modified. Here, the netlist is a file extracted from the schematic tool. This netlist is used for simulation or for layout versus schematic (LVS) comparison after the design of the semiconductor integrated circuit has been completed. The netlist represents connections between circuit devices included in the schematic circuit as well as connections between functional blocks (i.e., cells) formed of the circuit devices. [0005] Conventionally, during a pre-layout stage of the design of the semiconductor integrated circuit, a conventional device did not include a design unit for automatically connecting cells on a schematic circuit to generate interconnections (or wires). For this reason, a designer had to predict the path of the interconnection and then directly input a schematic circuit of the interconnection using a schematic editor of a schematic tool. Thus, the designer could model only a part of the parasitic resistance and the parasitic capacitance of the interconnection, which greatly affect the performance of the semiconductor integrated circuit. As a result, the work of designing the parasitic resistance and parasitic capacitance of the interconnection increases design costs and design time. Also, when a floor plan, which is schematic layout information of a semiconductor integrated circuit, was changed, it was difficult to change the parasitic resistance and parasitic capacitance of the interconnection. Therefore, in the pre-layout stage, it was difficult to perform a simulation on the semiconductor integrated circuit, considering the parasitic resistance and parasitic capacitance of the interconnection. [0006] Further, in a post-layout step of a semiconductor integrated circuit, when the semiconductor integrated circuit was simulated, a netlist file of an interconnection including parasitic resistance and parasitic capacitance, extracted from a layout of the semiconductor integrated circuit, was directly interfaced in a simulation device. Thus, when the semiconductor integrated circuit was simulated, errors such as a convergence error occurred often. Also, a lot of problems were caused when a control card was input or a probe sentence was inserted for analysis of the simulation results. Also, connections needed to be inconveniently tracked from the netlist having file formats other than the schematic circuit during the analysis of the simulation results. [0007] There is at present a layout design unit (e.g., a CAD tool), which automatically extracts the critical path of the designed semiconductor integrated circuit and then provides a simulation device with a netlist on the critical path. A designer designates an input port and an output port of the critical path. But, as the netlist input to the simulation device has a particular file format, if a schematic circuit is changed, the foregoing simulation method using the layout design unit may become inconvenient. Also, since the critical path is automatically extracted based on input information such as the input port and output port, the critical path considered by the designer may not be defined. Besides, the simulation method is applied to the full-chip of the semiconductor integrated circuit, and this may require a large simulation time. SUMMARY OF THE INVENTION [0008] The present invention provides a selective netlist generation device for generating a netlist of a selected cell in a schematic circuit and a method therefor. [0009] The present invention also provides a selective netlist generation device for generating a selective netlist including interconnection influence to be input in a simulation device using a schematic tool (or a selective netlist processor) in a pre-layout step, and a method therefor. [0010] The present invention further provides a selective netlist generation device for generating a selective netlist including interconnection influence to be input in a simulation device using a schematic tool (or a selective netlist processor) in a post-layout step, and a method therefor. [0011] The present invention still further provides a selective netlist generation device for generating a selective netlist including interconnection influence to be input in a simulation device using a schematic tool (or a selective netlist processor) in both a pre-layout step and a post-layout step. [0012] In accordance with a first aspect of the present invention, there is provided a selective netlist generation device for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit. The selective netlist generation device according to the present invention comprises a schematic circuit generation unit for generating a schematic circuit in response to input information including information on circuit devices included in respective cells, information on connections between the circuit devices, and schematic layout information of the cells, and a selective netlist output unit for selecting at least one cell included in the schematic circuit and generating a netlist of the selected cell, in response to selection information. [0013] In accordance with a second aspect of the present invention, there is provided a selective netlist generation device for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit. The selective netlist generation device according to one embodiment of the present invention includes a selective netlist processor for generating a selective netlist of a schematic circuit including cells, a simulation schematic circuit obtained by combining the schematic circuit and an interconnection schematic circuit, and cells performing specific operations of the simulation schematic circuit, in response to input information. This input information includes information on circuit devices included in the respective cells, information on connections between the circuit devices, and schematic layout information of the cells, information on interconnections interconnecting the cells, and selection information for selecting cells performing specific operations among the cells. The selective netlist generation device further includes an interconnection generator for generating interconnections in response to positional information of cells included in the schematic circuit and providing information on the generated interconnections to the selective netlist processor. [0014] The selective netlist processor may include a schematic circuit generation unit for generating the schematic circuit in response to the input information; an interconnection schematic circuit generation unit for generating a schematic circuit of the interconnections in response to the information on the interconnections; a simulation schematic circuit generation unit for combining first ports included in the cells of the schematic circuit with second ports of the interconnection schematic circuit, corresponding to the first ports, to generate the simulation schematic circuit; and a selective netlist output unit for selecting cells performing specific operations of the simulation schematic circuit and generating a selective netlist of the selected cells. [0015] The schematic circuit generated by the interconnection schematic circuit generating circuit should maintain positional relations between the cells and includes a hybrid .pi. model. Moreover, the non-selected cells connected to the cells selected by the selection information via the interconnections are used as capacitance devices. [0016] In accordance with a third aspect of the present invention, there is provided a selective netlist generation device for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit. The selective netlist generation device includes a selective netlist processor for generating a selective netlist of a schematic circuit including cells, a simulation schematic circuit obtained by combining the schematic circuit and an interconnection schematic circuit, and cells performing specific operations of the simulation schematic circuit, in response to input information. The input information includes information on circuit devices included in the respective cells, information on connections between the circuit devices, and schematic layout information of the cells, a netlist of parasitic resistance and parasitic capacitance, which are parasitic on the layout of the interconnections interconnecting the cells, and selection information for selecting cells performing specific operations among the cells. The selective netlist generation device further includes a layout generator for generating a layout of the semiconductor integrated circuit in response to the information on the schematic circuit, provided from the selective netlist processor, and a parasitic RC extractor for extracting a netlist of the parasitic resistance and parasitic capacitance, which are parasitic on the layout of the interconnections, generated from the layout generator, and providing the extracted netlist to the selective netlist processor. [0017] The selective netlist processor may also include a schematic circuit generation unit for generating the schematic circuit in response to the input information; an interconnection schematic circuit generation unit for generating the schematic circuit of the interconnections in response to the netlist of the parasitic resistance and parasitic capacitance; a simulation schematic circuit generation unit for combining first ports included in the cells of the schematic circuit and second ports of the interconnection schematic circuit corresponding to the first ports to generate the simulation schematic circuit; and a selective netlist output unit for selecting cells performing specific operations of the simulation schematic circuit and generating a selective netlist of the selected cells. [0018] In accordance with a fourth aspect of the present invention, there is provided a selective netlist generation device for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit. The selective netlist generation device may include a selective netlist processor for generating a selective netlist of a schematic circuit including cells, a first simulation schematic circuit obtained by combining the schematic circuit and an interconnection schematic circuit, a second simulation schematic circuit obtained by combining the schematic circuit and a schematic circuit corresponding to a netlist of parasitic resistance and parasitic capacitance, and cells performing specific operations of the simulation schematic circuit, in response to input information. The input information includes information on circuit devices included in the respective cells, information on connections between the circuit devices, schematic layout information of the cells, information on the interconnections interconnecting the cells, and selection information for selecting cells performing specific operations among the cells. The selective netlist generation device further includes an interconnection generator for generating the interconnections in response to positional information of the cells and providing the generated information on the interconnections. A layout generator is also provided. The layout generator is configured to generate a layout generator for generating a layout of the semiconductor integrated circuit in response to the information on the schematic circuit provided from the selective netlist processor. A parasitic RC extractor may also be provided. The parasitic RC extractor extracts a netlist of the parasitic resistance and parasitic capacitance, which is parasitic on the layout of the interconnections, generated from the layout generator, and provides the extracted netlist to the selective netlist processor. [0019] The selective netlist generation device may combine the selective netlist of the parasitic resistance and parasitic capacitance, which are parasitic on the layout of the cells extracted by the parasitic RC extractor, with the selective netlist of the selected cells, to generate a combined selective netlist. [0020] In some further embodiments of the present invention, cells and interconnections for analyzing specific operations can be selected in the simulation schematic circuit including the parasitic resistance and parasitic capacitance of the interconnections. Accordingly, various simulations can be analyzed quite accurately, and the time required for the simulation of a semiconductor integrated circuit can be effectively reduced. Also, in the selective netlist generation device and the method therefor according to the present invention, the parasitic RC interconnections generated in a pre-layout step or in a post-layout step are generated as the schematic circuit and then interfaced in a simulation device. As a result, as compared to the case that the netlist of the parasitic RC interconnection is interfaced as a file in the simulation device, errors caused by the designer can be reduced. Also, the present invention allows the designer to accurately analyze modeling of the parasitic resistance and parasitic capacitance. Further, it becomes easier for the designer to insert a variety of simulation options into the schematic circuit. Continue reading... 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