Methods and systems for memory devices

Title: Methods and systems for memory devices

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20080144391, Methods and systems for memory devices.

1. A method for accessing a flash memory cell, comprising: erasing at least one bit of the memory cell; and after erasing the at least one bit of the memory cell, performing a soft program operation to bias the memory cell thereby improving the reliability of data stored in the memory cell.

2. The method of claim 1, wherein erasing the at least one bit comprises: injecting a number of charged carriers into a charge trapping dielectric layer of the memory cell to adjust a threshold voltage of the memory cell.

3. The method of claim 2, wherein performing a soft program operation comprises: adjusting the threshold voltage of the memory cell by biasing the memory cell to adjust the number of charged carriers in the charge trapping dielectric layer.

4. The method of claim 3, wherein the memory cell is a flash memory cell.

5. The method of claim 3, wherein the memory cell is a flash memory cell that is configured to store at least two bits of data.

6. The method of claim 1, wherein the soft program operation comprises: applying a first wordline voltage having a first polarity to one or more wordlines associated with the one or more memory cells; and concurrently applying a first channel voltage having a second polarity to one or more channel regions associated with the one or more memory cells.

7. The method of claim 6, wherein erasing the at least one bit of one or more memory cells comprises: applying a second wordline voltage having the second polarity to the one or more wordlines; and concurrently applying a second channel voltage having the first polarity to the one or more channel regions.

8. The method of claim 1, wherein the soft program operation comprises: applying a negative voltage to one or more channel regions respectively associated with the one or more memory cells.

9. The method of claim 1, wherein the soft program operation comprises: applying a negative voltage to one or more channel regions respectively associated with the one or more memory cells; and concurrently applying a positive voltage to one or more wordlines respectively associated with the one or more memory cells.

10. A method for accessing a flash memory cell having a channel region disposed between a source and a drain, and a wordline disposed over the channel region, the method comprising: erasing a bit of the flash memory cell by applying a first wordline voltage having a first polarity to the wordline while concurrently applying a first channel voltage to the channel region; and improving the reliability of data stored in the flash memory cell by applying a second wordline voltage having a second polarity to the wordline while concurrently applying a second channel voltage having the first polarity to the channel region.

11. The method of claim 10, wherein improving the reliability of the data further comprises at least one of: applying a source voltage having the second polarity to the source; or applying a drain voltage having the second polarity to the drain.

12. The method of claim 10, further comprising: applying a high-magnitude voltage having the second polarity to a deep-well that electrically isolates the channel region from a substrate on which the flash memory cell is formed.

13. The method of claim 10, further comprising: programming the bit of the flash memory cell by applying a third wordline voltage having the second polarity to the wordline while concurrently applying a source-drain voltage between the source and drain.

14. The method of claim 13, further comprising: applying a high-magnitude voltage having the second polarity to a deep-well that electrically isolates the channel region from a substrate on which the flash memory cell is formed.

15. A method for accessing a memory cell having a channel region disposed between a source and a drain, and a wordline disposed over the channel region, the method comprising: erasing a bit of the memory cell by applying a first wordline voltage having a first polarity to the wordline while concurrently applying a first channel voltage to the channel region; and improving the reliability of data stored in the memory cell by applying a second wordline voltage having a second polarity to the wordline while concurrently applying a source voltage having the first polarity to a source region.

16. The method of claim 15, further comprising: while the second wordline voltage is applied to the wordline, concurrently applying a second channel voltage having the first polarity to the channel region.

17. A memory device formed over a substrate, comprising: an array of memory cells; wherein an individual memory cell of the array comprises: a channel region disposed between a buried bitline source and a buried bitline drain, and a wordline disposed over the channel region; a well under a set of individual memory cells, wherein at least a portion of the well coincides with the channel region; and well selection circuitry configured to selectively bias the well to a positive voltage or a negative voltage.

18. The memory device of claim 17, further comprising: source bit line selection circuitry configured to selectively bias the buried bitline source to a positive or a negative voltage.

19. The memory device of claim 18, wherein the well and the buried bitline source can be biased independently of one another.

20. The memory device of claim 18, further comprising: a deep-well under the well configured to isolate the well from the substrate; and deep-well circuitry configured to provide a high-magnitude voltage on the deep-well.

Brief Patent Description - Full Patent Description - Patent Claims

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Previous Patent Application:
Word line driver design in nor flash memory
Next Patent Application:
Methods for reducing write time in nonvolatile memory devices and related devices
Industry Class:
Static information storage and retrieval

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