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  Methods and systems for inspection of wafers and reticles using designer intent dataUSPTO Application #: 20080081385Title: Methods and systems for inspection of wafers and reticles using designer intent data Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer. (end of abstract) Agent: Baker & Mckenzie LLP - New York, NY, US Inventors: Paul Frank Marella, Sharon McCauley, Ellis Chang, William Volk, James Wiley, Sterling Watson, Sagar A. Kekare, Carl Hess USPTO Applicaton #: 20080081385 - Class: 438014000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, With Measuring Or Testing The Patent Description & Claims data below is from USPTO Patent Application 20080081385. Brief Patent Description - Full Patent Description - Patent Application Claims
PRIORITY CLAIM [0001] This application claims priority to U.S. Provisional Application No. 60/485,338 entitled "Methods and Systems for Inspection of Wafers and Reticles Using Designer Intent Data," filed Jul. 3, 2003, which is incorporated by reference as if fully set forth herein. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention generally relates to methods and systems for inspection of wafers and reticles using designer intent data. Certain embodiments relate to systems and methods for detecting defects on a wafer based on data representative of a reticle or data produced by inspection of a reticle. [0004] 2. Description of the Related Art [0005] Fabricating semiconductor devices such as logic and memory devices typically includes processing a specimen such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that typically involves transferring a pattern to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices. [0006] During each semiconductor fabrication process, defects such as particulate contamination and pattern defects may be introduced into semiconductor devices. Such defects may be found either randomly on a specimen surface or may be repeated within each device formed on a specimen. For example, random defects may be caused by events such as an unexpected increase in particulate contamination in a manufacturing environment and an unexpected increase in contamination in process chemicals that may be used in fabrication of a semiconductor device. [0007] Defects may also be formed in a systematic fashion over time and due to individual process marginalities and interactions of multiple processes. Defects caused by individual process marginalities or by interactions between multiple processes may result in defects such as a film thickness variation or a lateral dimension variation due to dose variation. Such defects may, in turn, result in a defect in a semiconductor device formed on the specimen such as bridging between two conductive structures thereby forming a short between the structures. Defects repeated within each semiconductor device formed on an entire specimen may, for example, be systematically caused by contamination or defects found on a reticle, or a mask. Contamination or defects on a reticle may be transferred along with a device pattern to a resist during a lithography process. [0008] As the dimensions of advanced semiconductor devices continue to shrink, the presence of defects in the semiconductor devices limits the successful fabrication, or yield, of a semiconductor device. For example, a reticle defect reproduced in a resist patterned during lithography may cause an open circuit or a short circuit in a semiconductor device formed in subsequent processing. Because fabrication of a semiconductor device includes many complex process steps, the adverse effects of defects on total yield may increase exponentially if an error that is caused by a defect is propagated throughout an entire manufacturing process or operation over time. SUMMARY OF THE INVENTION [0009] An embodiment of the invention relates to a computer-implemented method that includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle. The reticle is used to form a pattern on the wafer prior to inspection of the wafer. The nuisance defects may be formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects. In one embodiment, the nuisance defects may be formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects based on designer intent data. In further embodiments, if the nuisance defects are formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects, the method may include analyzing the nuisance defects to determine if the permissible reticle defects were correctly classified. In some embodiments, if the permissible reticle defects were not correctly classified, the method may include determining if the reticle should be analyzed, reworked, or disposed. In another embodiment, the method may include determining if the nuisance defects will affect yield of semiconductor devices, which will be formed on the wafer. [0010] In some embodiments, the method may include separating the nuisance defects from actual defects on the wafer. Such embodiments may also include processing data representative of the actual defects, but not the nuisance defects. In additional embodiments, the method may include generating a two-dimensional map of the wafer. The nuisance defects may be distinguished from other defects in the map by one or more different designations. [0011] In another embodiment, the method may include transmitting the inspection data from an inspection system used to perform the inspection of the reticle to a processor configured to perform the method. In a different embodiment, the method may include transmitting the inspection data from a fab database to a processor configured to perform the computer-implemented method. In one such embodiment, transmitting the inspection data may include sending coordinates of defects detected on the reticle and images of the defects. In an additional embodiment, if the inspection data includes coordinates of a location of a defect on the reticle, the method may include translating the coordinates of the location of the defect to coordinates of locations of one or more of the nuisance defects on the wafer. The method may include any other steps of any of the methods described herein. [0012] An additional embodiment relates to a computer-implemented method that includes identifying locations on a wafer in which nuisance defects will be formed based on inspection data produced by inspection of a reticle. In one embodiment, the method may also include selecting one or more parameters for wafer inspection such that the locations of the nuisance defects are not inspected. In a different embodiment, the method may include selecting one or more parameters for wafer defect review such that the nuisance defects are not reviewed. In another embodiment, the method may include selecting one or more parameters for wafer defect analysis such that the nuisance defects are not analyzed. [0013] Another embodiment relates to a computer-implemented method that includes identifying critical portions of a wafer based on the criticality associated with different areas of the wafer. The method also includes selecting parameters for inspection of the wafer such that only the critical portions of the wafer are inspected. In some embodiments, the parameters may be selected such that nuisance defects on the wafer are not classified as actual defects. In one embodiment, the parameters may be selected such that critical portions of the wafer having different criticalities are inspected with different parameters. According to another embodiment, the method may include setting one or more parameters for classification of defects on the wafer based on the criticality of the critical portions. [0014] In another embodiment, the method may include assigning a designation to a defect on the wafer based on the criticality of the critical portion in which the defect is located. In a different embodiment, the method may include determining processing of a defect on the wafer based on the criticality of the critical portion in which the defect is located. In some embodiments, the method may include classifying defects on the wafer as critical defects or non-critical defects and analyzing a process performed on the wafer based on the critical defects and the non-critical defects. In another embodiment, the method may include classifying defects on the wafer as critical defects or non-critical defects and processing the critical defects separately from the non-critical defects. [0015] According to an additional embodiment, the method may include discarding inspection data representing defects in one of the critical portions if the defects have a lateral dimension smaller than a predetermined threshold and if other features in the one portion have a lateral dimension greater than the predetermined threshold. In a different embodiment, the method may include discarding inspection data representing defects in one of the critical portions if an element of a circuit in the one portion has a predetermined amount of redundancy and if the defects in the one portion do not exceed a predetermined density threshold. [0016] In some embodiments, the method may include translating coordinates of a location of a defect detected on a reticle to coordinates of locations of one or more defects on the wafer. Such an embodiment may also include analyzing the printability of the defect detected on the reticle. In another such embodiment, the method may include removing inspection data at the coordinates on the wafer from the wafer inspection data. [0017] In one embodiment, the method may include generating one or more two-dimensional maps illustrating the critical portions of the wafer. The inspection may be performed on one level of the wafer. In one embodiment, the method may include identifying the criticality of a defect on the wafer based on the criticality of the critical portion in which the defect is located and data representative of at least one layer of the wafer above or below the one level. In another embodiment, the method may include generating a three-dimensional representation of the defect, the one level, and at least the one layer of the wafer above or below the one level. [0018] A further embodiment relates to a computer-implemented method that includes determining one or more parameters for wafer defect review based on the criticality associated with different areas of the wafer. In one embodiment, the method may include selecting the one or more parameters such that only defects located in critical portions of the wafer are reviewed. In one such embodiment the one or more parameters may be different for one or more of the critical portions. In another embodiment, the method may include sending information about the criticality of the different areas of the wafer to a tool configured to perform the wafer defect review. [0019] Another embodiment relates to a computer-implemented method that includes determining one or more parameters for wafer defect analysis based on the criticality associated with different areas on the wafer. The method may include selecting the one or more parameters such that only defects located in critical portions of the wafer are analyzed in some embodiments. In such an embodiment, the one or more parameters may be different for one or more of the critical portions. In other embodiments, the method may include sending information about the criticality of the different areas of the wafer to a tool configured to perform the wafer defect analysis. [0020] An additional embodiment relates to a computer-implemented method that includes identifying bad die on a wafer. In an embodiment, identifying the bad die may include performing functional testing on the wafer after a manufacturing process used to process the wafer is completed. The bad die may contain one or more electrical elements having functionality outside of a predetermined range. The method also includes identifying a first portion of defects and a second portion of defects on the wafer based on data generated by inspection of the wafer in combination with information representative of a design of the one or more electrical elements. In one embodiment, the data generated by inspection of the wafer may include data generated by multiple inspections of the wafer, which may be performed at different times during the manufacturing process. The first portion of the defects may alter a characteristic of a device formed by the one or more electrical elements such that the characteristic is outside of the predetermined limits. In addition, the method may include determining a property of the manufacturing process based on the first portion of the defects. In one embodiment, the property may be a kill ratio of the first portion of the defects. In a different embodiment, the property may be a yield of the manufacturing process. In some embodiments, the method may include altering one or more parameters of the manufacturing process based on the property. The method may further include any other steps of any of the methods described herein. [0021] A further embodiment relates to a computer-implemented method that includes altering a design of an integrated circuit (IC) based on data generated by inspection of a wafer during a manufacturing process. The data generated by inspection of the wafer includes information about defects detected on the wafer, and a substantial portion of the defects includes critical defects that can alter one or more characteristics of the IC. For example, the method may include distinguishing between the critical defects and other noncritical defects detected during the inspection based on the design. The non-critical defects are defects that will not substantially alter the one or more characteristics of the IC. Continue reading... Full patent description for Methods and systems for inspection of wafers and reticles using designer intent data Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Methods and systems for inspection of wafers and reticles using designer intent data patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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