| Methods and systems for electroplating wafers -> Monitor Keywords |
|
|
  Methods and systems for electroplating wafersUSPTO Application #: 20060191784Title: Methods and systems for electroplating wafers Abstract: Improved methods and systems for electroplating wafers are described herein. The method includes the acts of introducing a wafer which is coupled to an electrode into an electroplating cell having a counter electrode; maintaining a flow of a plating solution through the cell for electroplating the wafer; removing the wafer from the cell; stopping the flow of the plating solution through the cell; maintaining a volume of plating solution within the cell sufficient to keep the counter electrode submerged during stoppage of flow; removing the plating solution within the cell; and repeating the above steps for a subsequent wafer. By stopping the flow of plating solution after completion of plating one or more wafers, a consumption rate of additives enhancing electroplating properties is reduced, a production rate of breakdown products produced during electroplating is reduced, plating solution useable life is increased, and a need for plating solution analysis is reduced. (end of abstract) Agent: John J. Oskorep, Esq. One Magnificent Mile Center - Chicago, IL, US Inventors: Robert William Hitzfeld, Jennifer Ai-Ming Loo, Murali Ramasubramanian USPTO Applicaton #: 20060191784 - Class: 204198000 (USPTO) Related Patent Categories: Chemistry: Electrical And Wave Energy, Apparatus, Electrolytic, Object Protection, Work Conveyer The Patent Description & Claims data below is from USPTO Patent Application 20060191784. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates generally to methods and systems for electroplating substrates, such as those utilized for damascene electroplating of write coils in magnetic heads. [0003] 2. Description of the Related Art [0004] The demand for manufacturing semiconductor integrated circuit (IC) devices, such as computer chips with high circuit speed, high-packing density, and low power dissipation, requires the downward scaling of feature sizes in ultra-large-scale integration (ULSI) and very-large-scale integration (VLSI) structures. The trend to smaller chip sizes and increased circuit density requires the miniaturization of interconnect features which severely penalizes the overall performance of the structure because of increasing interconnect resistance and reliability concerns such as fabrication of the interconnects and electromigration. Magnetic heads with inductive write coils also feature miniaturization requirements to increase areal storage densities on magnetic disks and reduction of coil resistance. [0005] Historically, such structures have utilized aluminum and aluminum alloys as the metallization on silicon wafers, with silicon dioxide being the dielectric material. In general, openings were formed in the silicon dioxide dielectric layer in the shape of vias and trenches which were then metallized to form the interconnects. Increased miniaturization, however, has required these openings to be at submicron sizes (e.g., 0.5.mu. and lower). To achieve such miniaturization, industries have moved to the use of copper instead of aluminum as the metal to form the connection lines and interconnects in the chip. Copper has a lower resistivity than aluminum and the thickness of a copper line for the same resistance can be thinner than that of an aluminum line. Copper-based interconnects therefore represent the most foreseeable future trend in the fabrication of such devices. Copper can be deposited on substrates by plating (such as electroless and electrolytic), sputtering, plasma vapor deposition (PVD), and chemical vapor deposition (CVD). It is generally recognized that a plating-based deposition is the best method to apply copper to the device since it can provide high deposition rates and low system costs. [0006] Referring to FIG. 1, a plating system 100 of the prior art is shown. Plating system 100 is used for electroplating copper onto a wafer 112 which is coupled to a cathode. Plating system 100 may be of the type provided by Semitool, Inc. of Kalispell, Mont., U.S.A., for example, the EQUINOX.RTM. system platform (EQUINOX is a registered trademark of Semitool, Inc.). System 100 includes an electroplating cell 110 which holds a plating solution 127. Cell 110 is made of a suitable material, such as plastic or other material inert to plating solution 127. Cell 110 is preferably cylindrical in shape, but alternatively may be square or rectangular in shape. Wafer 112 is horizontally disposed at the upper part of cell 110 and may be any type substrate, such as a silicon, ceramic or other material having openings including trenches and vias to be plated. A wafer surface 112a of wafer 112 is typically coated with a seed layer of copper or other metal to initiate plating thereon. A copper seed layer may be applied by sputtering, plasma vapor deposition (PVD), chemical vapor deposition (CVD), or the like. An anode 113 is preferably circular for wafer plating and is horizontally disposed at the lower part of cell 110, forming a space therein between wafer 112 and anode 113. Anode 113 is a soluble electrode which is consumed during processing. Suitable soluble anodes include copper and other copper alloys such as copper phosphate. The anode and cathode are electrically connected by wiring 114 and 115, respectively, to a power supply 116. In electroplating system 100, wafer 112 has a negative charge so that copper ions in the solution are reduced to form plated copper metal on wafer surface 112a. An oxidation reaction takes place at anode 113 causing copper metal to go into solution. [0007] Plating system 100 further includes a plating solution holding tank 119 from which a plating solution 127 is drawn via a pump 122 through a plating solution inlet transport line 117, a flow measurement device 151, and an inlet valve 140 to an inlet 110a of cell 110. Plating solution 127 flows through cell 110 and thereby contacts wafer 112 and anode 113, filling the space therein between them with the solution. A rotor 130 holds wafer 112 in position and a rotor 131 holds anode 113 in place. Rotors 130 and 131 alternatively may be a flange, plate, or other similar device. Plating solution 127 exits cell 110 through an overflow weir 125 into outlet 110b and is recycled into tank 119 through a plating solution transport line 118. During operation of plating system 100 to plate wafer 112, plating solution 127 continuously flows through the system at a predetermined plating flow rate. The plating flow rate may be, for example, between 2 to 6 gallons per minute (g/m). This forms a substantially uniform electrolyte composition in the system and contributes to the overall effectiveness of the wafer plating. Flow of plating solution 127 through plating system 100 is controlled by a flow control mechanism which includes pump 122 and inlet valve 140. Additionally, the flow control mechanism includes a flow measurement device 151, such as a flow meter, and a closed feedback loop 150 for more precise control over the flow of plating solution 127. [0008] During operation of plating system 100, copper metal is plated on wafer surface 112a when power supply 116 is energized. A pulse current, direct current (DC), reverse periodic current, or other suitable current may be employed. The electroplating process results in depletion of the copper concentration of plating solution 127. Copper deposits must be uniform and capable of filling the extremely small trenches and vias of the device. These important properties are typically achieved using multi-component plating solutions, which include organic and inorganic components. Typical plating solution 127 formulations use highly stable electrolytes containing copper sulfate and sulfuric acid. As an example, copper concentration in these electrolytes may be between 12-60 grams/liter (g/l) and sulfuric acid 1-240 g/l. [0009] Other components added to the plating solution are present in relatively small amounts. These components are organic additives and chloride ions. The organic additives, depending on the concentration and chemical composition, affect the properties of the electrodeposited copper including uniformity, hardness, ductility, tensile strength, grain size, etc. These additives for enhancing electroplating properties, which react at the wafer surface during electroplating, fall into three major categories. Accelerators are compounds that contain pendant sulfur atoms that locally accelerate deposition where they are adsorbed. Suppressors are polymers, such as polyethylene glycols, which have the ability to form a current-suppressing film on the entire wafer surface. The third category of organic additives are levelers, which are secondary suppressors and work only on the protruding surfaces where mass transfer is most effective. [0010] After completing the electroplating of one or more wafers, the flow through pump 122 is set and maintained at a reduced "idle flow" rate. This reduced idle flow rate may be, for example, between 1 to 1.5 g/m. During this time period, no wafers are being electroplated. At some point in time, however, subsequent wafers will be electroplated where pump 122 is once again set and maintained at the higher plating flow rate. [0011] In addition to reacting at the surface of the wafer during electroplating, the additives of the plating solution undesirably react at the surface of anode 113 within cell 110 during electroplating and idle flow during non-plating periods. Further, there are other interactions between the additives and inorganic compounds which cause decomposition and modification of initial organic compounds. These breakdown products ideally need to be kept below a threshold level in order to provide the most uniform of copper deposition and highest capability of filling the extremely small trenches and vias of the device. Thus, monitoring these breakdown products must be performed at least once every four to six hours by analyzing the composition of the bath during idle flow. Also, replacement of up to 20% may be done daily to maintain the plating solution in steady state. Both of these requirements result in a large amount of time and labor for plating solution analysis and control. This is especially true when system utilization is less than 100%. [0012] Accordingly, what are needed are improved methods for electroplating wafers as well as improved systems for performing such methods. SUMMARY [0013] Improved methods and systems for electroplating wafers are described herein. The method includes the acts of introducing a wafer which is coupled to an electrode (e.g. a cathode) into an electroplating cell having a counter electrode (e.g. an anode); maintaining a flow of a plating solution through the cell for electroplating the wafer; removing the wafer from the cell; stopping the flow of the plating solution through the cell; maintaining a volume of plating solution within the cell sufficient to keep the counter electrode submerged during stoppage of flow; removing the plating solution within the cell; and repeating the above steps for a subsequent wafer. [0014] By stopping the flow of plating solution after completion of plating one or more wafers, a consumption rate of additives enhancing electroplating properties is reduced, a production rate of breakdown products produced during electroplating is reduced, plating solution useable life is increased, and a need for plating solution analysis is reduced. BRIEF DESCRIPTION OF THE DRAWINGS [0015] For a fuller understanding of the nature and advantages of the present invention, as well as the preferred mode of use, reference should be made to the following detailed description read in conjunction with the accompanying drawings: [0016] FIG. 1 is a system for electroplating wafers of the prior art; [0017] FIG. 2 is a flowchart which describes an improved method for electroplating wafers in accordance with the present invention; [0018] FIG. 3 is a system for electroplating wafers in accordance with the present invention; and [0019] FIG. 4 is a system for electroplating wafers according to a preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0020] In describing the preferred embodiment of the present invention, reference will be made herein to FIGS. 1-4 of the drawings in which like numerals refer to like features of the invention. Features of the invention are not necessarily shown to scale in the drawings. Continue reading... Full patent description for Methods and systems for electroplating wafers Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Methods and systems for electroplating wafers patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Methods and systems for electroplating wafers or other areas of interest. ### Previous Patent Application: Method and apparatus for forming adherent metal film on a polymer substrate Next Patent Application: Mineral water generator Industry Class: Chemistry: electrical and wave energy ### FreshPatents.com Support Thank you for viewing the Methods and systems for electroplating wafers patent info. IP-related news and info Results in 0.65264 seconds Other interesting Feshpatents.com categories: Canon USA , Celera Genomics , Cephalon, Inc. , Cingular Wireless , Clorox , Colgate-Palmolive , Corning , Cymer , |
||
