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Methods and devices for dram initializationRelated Patent Categories: Electrical Computers And Digital Processing Systems: Support, Digital Data Processing System Initialization Or Configuration (e.g., Initializing, Set Up, Configuration, Or Resetting)Methods and devices for dram initialization description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060010313, Methods and devices for dram initialization. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND [0001] The present disclosure relates in general to devices and methods for DRAM initialization. In particular, the present disclosure relates to devices and methods for DRAM initialization according to initialization parameters stored when DRAM are not removed. [0002] Computers generally comprise a CPU, chipsets, a memory controller and buses. CPU processes most operations of the computer. Chipsets support the operation of the CPU. Generally, the chipset comprises controllers for transmission of data between the CPU and other devices. The memory controller is a part of the chipset, establishing data transmission between memory and the CPU. Buses are connected between the CPU, memory, and other I/O devices. The bus determines the operating speed of a main board. In response to different data transmission requirements, different kinds of buses are provided. A memory bus is connected between the memory controller and the memory module. [0003] During boot, memory initialization is performed, comprising setting memory operating frequency and a column address strobe latency (CL). [0004] Conventional technology obtains memory initialization parameters by reading serial presence detect (SPD) codes stored in EEPROM of the memory. Thereby, information required for memory initialization is obtained. [0005] Using double data rate-synchronous DRAM (DDR) as an example, the operating frequency of the DDR can be 400 MHz, 333 MHz and 266 MHz, and column address strobe latency (CL) of the DDR can be 3 clocks, 2.5 clocks and 2 clocks. BIOS can initialize the DDR operating at 400 MHz and 2.5 CL according to SPD. [0006] Boot is delayed by determination of the information required for initialization of memory, performed at each boot. However, when memory is not removed between consecutive boots, determination of the information for memory initialization at subsequent boot is unnecessary since determination is the same. SUMMARY [0007] Methods and devices for DRAM initialization are provided. An embodiment of a method for DRAM initialization of a computer system comprises: storing initialization parameters of at least one memory, detecting conditions of the memory, reading the conditions of the memory to initialize memory during boot, when conditions of the memory have not changed. [0008] Another embodiment of a device for DRAM initialization of a computer system comprises at least one memory, a detection circuit detecting conditions of the memory, and outputting a fast initialization signal, a buffer storing initialization parameters of at least one memory, a memory controller setting the initialization parameters according to memory information, and reading the conditions of the memory to initialize the memory when boot the computer system and receiving the fast initialization signal. DESCRIPTION OF THE DRAWINGS [0009] The invention will be more fully understood from the detailed description, given hereinbelow, and the accompanying drawings. The drawings and description are provided for purposes of illustration only and, thus, are not intended to limit the invention. [0010] FIG. 1 is a schematic diagram of an embodiment of a computer. [0011] FIG. 2A is a circuit diagram of an embodiment of detection circuit. [0012] FIG. 2B is a true table of the voltage levels against specific terminals of detection circuit shown in FIG. 2A. [0013] FIG. 3 is a flowchart showing an embodiment of a method for DRAM initialization. DETAILED DESCRIPTION [0014] FIG. 1 is a schematic diagram of an embodiment of a computer 10 comprising CPU 12, cache memory 14, memory controller 16, I/O chipset 17 and I/O interface (18A.about.18D). Computer 10 further comprises buses 19 connected between the devices thereof. Memory 20A.about.20D may be respectively installed in four dual in-line memory modules (DIMM). In addition, detection circuit 22 detects whether at least one memory 20A.about.20D is changed. In some embodiments, the detection circuit 22 detects removal of memory from the DIMM. In addition, buffer 21 stores initialization parameters of the memory. In some embodiments, buffer 21 can be located in the Southbridge chipset. [0015] FIG. 2A is a circuit diagram of an embodiment of detection circuit 22. FIG. 2B is a true table of the voltage levels against specific terminals of detection circuit 22 shown in FIG. 2A. [0016] Detection circuit 22 comprises comparator 24 and D-type flip-flops 26A and 26B. In some embodiments, comparator 24 can be a XOR logic gate, with terminal A.sub.0 representing status of memory 20A. The logic level of terminal A.sub.0 is "0" when memory 20A is plugged in the memory module, "1" when memory 20A is removed from the memory module. In addition, as shown in FIG. 1, four terminals A.sub.0.about.A.sub.3 respectively represent terminals of memory 20A.about.20D. FIG. 2A only shows the detection circuit of memory 20A. [0017] In FIG. 2A, the initial values of output terminals Q.sub.0 and Q.sub.1, respectively, of D-type flip-flops 26A and 26B are "1" because a predetermined voltage 3.3V.sub.SUS is applied thereto. As memory 20A does not exist, the logic level of terminal A.sub.0 and nodes B.sub.0 and C.sub.0 are high "1", terminal E.sub.0 thus outputs low logic level "0". [0018] As memory 20A is installed, the logic level of terminal A.sub.0 is at low "0", inverted by inverter 27 and input to D-type flip-flops 26A. Thus, the logic level of terminal B.sub.0 is at low "0", and that of terminal C.sub.0 is still at high "1". Thus, terminal E.sub.0 outputs high logic level "1" because the logic levels of terminals A.sub.0 and C.sub.0 are different. [0019] In addition, the high logic level "1" of terminal E.sub.0 enables D-type flip-flops 26B. Thus, output terminal Q.sub.1 is at low logic level "0", and the logic level of terminal C.sub.0 becomes low "0". As the logic levels of terminal A.sub.0 and node C.sub.0 received by comparator 24 are the same, thus the logic level of terminal E.sub.0 is at low "0". [0020] As memory 20A is removed, the logic levels of terminal A.sub.0 and nodes B.sub.0 return to high "1", while that of terminal C.sub.0 remains at low "0". Thus, the logic levels of terminal A.sub.0 and node C.sub.0 received by comparator 24 are different, and the logic level of terminal E.sub.0 is at high "1". In some embodiments, the logic level of terminal E.sub.0 at high "1" represents output of a fast initialization signal. Continue reading about Methods and devices for dram initialization... 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