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  Methods and apparatus for dynamically reconfigurable parallel data error checkingUSPTO Application #: 20070234191Title: Methods and apparatus for dynamically reconfigurable parallel data error checking Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) transmitting data on a bus, wherein data is presented on the bus using varying widths; (2) configuring a cyclic redundancy check (CRC) to be performed on the data based on the manner in which the data is presented on the bus; and (3) performing the CRC on the data. Numerous other aspects are provided. (end of abstract)
Agent: Ibm Corporation, Intellectual Property Law - Rochester, MN, US Inventors: Mark J. Hickey, Robert A. Shearer USPTO Applicaton #: 20070234191 - Class: 714799000 (USPTO) Related Patent Categories: Error Detection/correction And Fault Detection/recovery, Pulse Or Data Error Handling, Error/fault Detection Technique The Patent Description & Claims data below is from USPTO Patent Application 20070234191. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a division of and claims priority to U.S. patent application Ser. No. 11/016,217, filed Dec. 17, 2004, which is hereby incorporated by reference herein in its entirety for all purposes. FIELD OF THE INVENTION [0002] The present invention relates generally to processors, and more particularly to methods and apparatus for dynamically reconfigurable parallel data error checking. BACKGROUND [0003] Conventional logic performs continuous error checking, such as cyclic redundancy checking (CRC), on data presented in a fixed-width. However, such logic may not perform CRC on data presented in variable widths. Accordingly, methods and apparatus are desired for performing CRC on data presented in variable widths. SUMMARY OF THE INVENTION [0004] In a first aspect of the invention, a first method is provided. The first method includes the steps of (1) transmitting data on a bus, wherein data is presented on the bus using varying widths; (2) configuring a cyclic redundancy check (CRC) to be performed on the data based on the manner in which the data is presented on the bus; and (3) performing the CRC on the data. [0005] In a second aspect of the invention, a method is provided for checking data for errors. The method includes the steps of (1) transmitting one or more portions of one or more packets on a bus, wherein a length of each of the one or more packets are a multiple of a predetermined size and the bus width is a multiple greater than 1 of the predetermined size; (2) determining whether the bus is transmitting one or more portions of a plurality of packets; (3) if the bus is transmitting one or more portions of a plurality of packets, performing a cyclic redundancy check (CRC) on the one or more portions of each of the plurality of packets in parallel; and (4) if the bus is not transmitting one or more portions of a plurality of packets, (a) performing a CRC on the one or more portions of the packet transmitted on a first portion of the bus; and (b) performing a CRC on the one or more portions of the packet transmitted on a second portion of the bus based on a result of the CRC performed on the one or more portions of the packet transmitted on the first portion of the bus. [0006] In a third aspect of the invention, a first apparatus is provided. The first apparatus includes (1) a bus for transmitting data; (2) CRC logic, coupled to the bus, for performing CRC on data received from the bus; and (3) control logic, coupled to the bus and CRC logic, for providing control signals to the CRC logic. The first apparatus is adapted to (a) transmit data on the bus, wherein data is presented on the bus using varying widths; (b) configure a cyclic redundancy check (CRC) to be performed on the data based on the manner in which data is presented on the bus; and (c) perform the CRC on the data. [0007] In a fourth aspect of the invention, an apparatus is provided for checking data for errors. The apparatus includes (1) a bus for transmitting data packets, wherein the bus width is a multiple greater than 1 of a predetermined size; (2) CRC logic, coupled to the bus, for performing CRC on data packets received from the bus; and (3) control logic, coupled to the bus and CRC logic, for providing control signals to the CRC logic. The apparatus is adapted to (a) transmit one or more portions of one or more packets on the bus, wherein a length of each of the one or more packets are a multiple of the predetermined size; (b) determine whether the bus is transmitting one or more portions of a plurality of packets; (c) if the bus is transmitting one or more portions of a plurality of packets, perform a cyclic redundancy check (CRC) on the one or more portions of each of the plurality of packets in parallel; and (d) if the bus is not transmitting one or more portions of a plurality of packets, (i) perform a CRC on the one or more portions of the packet transmitted on a first portion of the bus; and (ii) perform a CRC on the one or more portions of the packet transmitted on a second portion of the bus based on a result of the CRC performed on the one or more portions of the packet transmitted on the first portion of the bus. Numerous other aspects are provided in accordance with these and other aspects of the invention. [0008] Other features and aspects of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings. BRIEF DESCRIPTION OF THE FIGURES [0009] FIG. 1 is a block diagram of an apparatus for checking data for errors in accordance with an embodiment of the present invention. [0010] FIG. 2 illustrates different ways in which one or more data packets are transmitted on a bus of the apparatus and corresponding values upon which control signals output by control logic of the apparatus are based in accordance with an embodiment of the present invention. [0011] FIG. 3 is a block diagram of exemplary CRC logic included in the apparatus for checking data for errors in accordance with an embodiment of the present invention. DETAILED DESCRIPTION [0012] The present invention provides methods and apparatus for performing continuous error checking, such as cyclic redundancy checking (CRC), on data. More specifically, according to the present methods and apparatus, logic may perform CRC on data presented in varying widths. For example, logic may receive one or more portions of one or more data packets from a bus of a predetermined width and perform CRC on the one or more data packets. [0013] FIG. 1 is a block diagram of an apparatus for checking data for errors in accordance with an embodiment of the present invention. With reference to FIG. 1, the apparatus 101 for checking data for errors includes a first processor (e.g., central processing unit (CPU)) 103 coupled to a second processor (e.g., graphics processing unit (GPU)) 105. Each processor 103, 105 is coupled to and/or includes respective transmit side logic 107, 109 for transmitting data (e.g., one or more portions of one or more data packets) from one processor 103, 105 and respective receive side logic 111, 113 for receiving data in the other processor 103, 105. Transmit side logic 109 of the second processor 105 may be coupled to receive side logic 111 of the first processor 103 by a bus 115 for transmitting data. In some embodiments, the bus 115 may be sixteen bytes wide for transmitting data packets with a granularity of eight bytes. Therefore, the bus 115 may transmit packets with total lengths that are any multiple of eight bytes (e.g., packets of varying lengths) from the second processor 105 to the first processor 103. One or more portions of such packets may be presented on the bus using varying widths (e.g., eight or sixteen bytes). Consequently, the bus 115 may transmit data in different ways, which are described below with reference to FIG. 2. For example, the bus 115 may be divided into multiple portions. A first portion may include the first eight bytes of the bus 115 and a second portion may include the second eight bytes of the bus 115. During operation, the first and second portions of the bus 115 may transmit one or more portions of the same packet or one or more portions of different packets, respectively. [0014] The above-described width of the bus 115, widths employed to present packets and granularity of packets transmitted on the bus 115 are exemplary. For example, a larger or smaller bus width, width employed to present packets and/or packet granularity may be employed. In some embodiments, the bus 115 may be divided into a larger number of portions. Further, although only a single bus is shown, the apparatus 101 for checking data for errors may include a larger number of buses for transmitting data packets (e.g., packets that may be presented on the bus in varying widths (variable-width data packets)). For example, the apparatus may include a second bus 125, which is similar to bus 115, coupling the transmit side logic 107 of the first processor 103 to the receive side logic 113 of the second processor 105. A separate instantiation of the first control logic 117, transmit CRC logic 119, second control logic 121 and receive CRC logic 123 (shown in phantom) may be coupled to the second bus 125. [0015] The apparatus 101 for checking data for errors includes first control logic 117 coupled to transmit CRC logic 119 both of which are coupled to the bus 115. The first control logic 117 is adapted to determine how a data packet is being transmitted on the bus 115 (e.g., by the transmit side logic 109), and based on how the data is being transmitted, provide control signals to the transmit CRC logic 119. The transmit CRC logic 119 is adapted to perform CRC on one or more portions of one or more such variable-width data packets. For example, the transmit CRC logic 119 may compute a pre-transfer CRC value of a variable-width data packet, insert the value into the variable-width data packet based on the control signals and transmit the variable-width data packet on the bus 115 to the first processor 103. [0016] Similarly, the apparatus 101 for checking data for errors includes second control logic 121 coupled to receive CRC logic 123 both of which are coupled to the bus 115, and therefore, coupled to the receive side logic 111 of the first processor 103. The second control logic 121 is adapted to determine a how a data packet is being transmitted on the bus 115 (e.g., by the transmit CRC logic 119), and based on how the data is transmitted, provide control signals to the receive CRC logic 123. The receive CRC logic 123 is adapted to perform CRC on one or more portions of one or more variable-width data packets. More specifically, based on the control signals, the receive CRC logic 123 may remove and store a transmitted pre-transfer (e.g., received) CRC value inserted into a received variable-width packet (e.g., by transmit CRC logic 119), compute a post-transfer CRC value from such variable-width data packet and compare the post-transfer CRC value with the pre-transfer (e.g., received) CRC value. If results of the CRC computed by the transmit CRC logic 119 matches the result of the CRC computed by the receive CRC logic 123, the variable-width data packet was successfully transmitted without error. However, if the CRC results do not match, an error may have occurred during data transmission. [0017] Details of the receive CRC logic 123 coupled to the first processor 103 are described below with reference to FIG. 3. The transmit CRC logic 119 may be similar to the receive CRC logic 123. However, as described above, the transmit CRC logic 119 computes and inserts a pre-transfer CRC value into a data packet and the receive CRC logic removes the pre-transfer (e.g., received) value from the data packet and computes a post-transfer CRC value. [0018] FIG. 2 illustrates different ways in which one or more data packets are transmitted on a bus of the apparatus and corresponding values upon which control signals output by control logic of the apparatus are based in accordance with an embodiment of the present invention. With reference to FIG. 2, table 201 illustrates different scenarios of data transmission on the bus 115 and corresponding values upon which control signals input by the receive CRC logic 119 are based. More specifically, the first column 203 (e.g., "1st 8 Bytes") of table 201 includes information about which portion of a variable-width data packet is transmitted on the first portion (e.g., first eight) bytes of the bus 115. The second column 205 (e.g., "crc_in") includes information about whether the CRC performed on the one or more portions of the variable-width data packet transmitted by the first portion of the bus 115 is based on an intermediate CRC value (e.g., a result of a CRC performed on a portion of the packet previously transmitted on the bus 115). The third column 207 (e.g., "data (48:63)") includes information whether the last two bytes of data transmitted on the first portion of the bus 115 are relevant to the CRC. More specifically, the third column 207 indicates, if the data transmitted on the first portion of the bus is not an end of packet, the last two bytes of data transmitted on the first portion of the bus represents data in the packet. However, if the data transmitted on the first portion of the bus is an end of packet, on the transmit side, zeroes are inserted into the last two bytes of data transmitted on the first portion of the bus before performing CRC on the transmit side, and on the receive side, zeroes are inserted to replace data in the last two bytes of data transmitted on the first portion of the bus before performing CRC on the transmit side. The fourth column 209 (e.g., "2nd 8 Bytes") of table 201 includes information about which portion of a variable-width data packet is transmitted on the second portion (e.g., last eight bytes) of the bus 115. The fifth column 211 (e.g., "crc_in") includes information about whether the CRC performed on the one or more portions of the variable-width data packet transmitted by the second portion of the bus 115 is based on an intermediate CRC value. The sixth column 213 (e.g., "data (48:63)") includes information whether the last two bytes of data transmitted on the second portion of the bus 115 are relevant to the CRC. More specifically, similar to the third column 207, the sixth column 213 indicates, if the data transmitted on the second portion of the bus is not an end of packet, the last two bytes of data transmitted on the second portion of the bus represents data in the packet. However, if the data transmitted on the second portion of the bus is an end of packet, on the transmit side, zeroes are inserted into the last two bytes of data transmitted on the second portion of the bus before performing CRC on the transmit side, and on the receive side, zeroes are inserted to replace data in the last two bytes of data transmitted on the second portion of the bus before performing CRC on the transmit side. [0019] In this manner, rows 215, 217, 219, 221, 223, 225, 227 of table 201 illustrate seven different ways in which data packets are transmitted on the bus 115 and corresponding values upon which control signals output by the second control logic 121 to the receive CRC logic 123 are based. Details of each row 215, 217, 219, 221, 223, 225, 227 of the table 201 are described below with reference to FIG. 3. Although table 201 illustrates seven different ways in which data packets are transmitted on the bus 115, a data packet may be transmitted on the bus 115 in a different way. Continue reading... Full patent description for Methods and apparatus for dynamically reconfigurable parallel data error checking Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Methods and apparatus for dynamically reconfigurable parallel data error checking patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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