| Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process -> Monitor Keywords |
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Method to increase charge retention of non-volatile memory manufactured in a single-gate logic processRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Variable Threshold (e.g., Floating Gate Memory Device)Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070170489, Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to non-volatile memory (NVM). More particularly, this invention relates to non-volatile memory cells fabricated using an ASIC or conventional logic process. In the present application, a conventional logic process is defined as a semiconductor process that implements single-well or twin-well technology and uses a single gate layer. This invention further relates to a method of operating a non-volatile memory to ensure maximum data retention time. BACKGROUND OF INVENTION [0002] Many modern integrated circuit applications demand the integration of non-volatile memory (NVM) and logic circuits on the same chip. However, traditional NVM cells are typically fabricated using a stacked gate structure or a split gate structure. Therefore, a typical NVM fabrication process requires the deposition of more than one gate layer. In contrast, logic circuits are typically fabricated using a semiconductor integrated circuit manufacturing process that involves the deposition of only one gate layer, which is deposited and patterned at the same time for all devices on the chip. Such a single-gate process is hereinafter referred to as a conventional logic process. Because the single-gate layer used in a conventional logic process typically includes polysilicon, this process is sometimes referred to as a single-poly process. [0003] The different requirements of traditional NVM circuits and logic circuits makes it difficult to fabricate both of these circuits on the same chip. The combination of an NVM circuit and a conventional logic circuit therefore typically requires the use of a much more complicated and expensive "merged non-volatile memory and logic" process, and results in a high wafer price. [0004] In order to resolve the NVM process integration challenge, various types of planar CMOS NVM structures have been proposed. Such NVM structures incorporate the single gate layer of the conventional logic process. More specifically, these NVM structures use patterned sections of the gate layer, which are left floating (i.e., have no associated gate contact, and are isolated from the substrate by a gate dielectric layer). These floating gates are selectively programmed or erased to store predetermined charges. Each floating gate passes over a respective read device (i.e., read transistor), whereby the charge stored on each floating gate alters the conduction properties of the associated read device. These conduction properties are sensed during the read operation. It is therefore essential that the charge stored on a floating gate manufactured in a conventional logic process is retained for as long as possible, thereby increasing the data retention time of the NVM system. [0005] FIG. 1 is a cross-sectional view of a conventional NVM cell 100 fabricated using a conventional logic process. NVM cell 100 is fabricated in substrate 101 and is isolated from other devices by field dielectric region 114. In a conventional logic process, field dielectric region 114 may be formed by filling a pre-etched substrate trench with dielectric, thereby forming a shallow-trench isolation (STI) region. NVM cell 100 includes source and drain contact diffusions 131 and 132, respectively, associated lightly doped source and drain extension diffusions 131A and 132A, gate dielectric layer 115, polysilicon floating gate 116, metal silicide regions 141-143 and dielectric sidewall spacers 105-106. Gate dielectric layer 115 (which is typically silicon dioxide) isolates floating gate 116 (which is typically heavily-doped poly-silicon) from substrate 101. Silicide regions 141, 142 and 143 are formed on the exposed upper surfaces of source contact region 131, drain contact region 132 and floating gate 116, respectively. Silicide regions 141-143 are formed in the following manner. A refractory metal layer is initially deposited over the upper surface of the NVM cell structure. Then, a reactive anneal is performed, which causes the metal layer to react with the underlying contacted silicon regions to form silicide regions 141-143. Next, a metal strip is performed, wherein the unreacted portions of the metal layer are removed, but silicide regions 141, 142, and 143 are not removed. Because silicide regions 141-143 are self-aligned with the underlying silicon regions, these layers are sometimes referred to as salicide (self-aligned silicide) regions. Modern logic processes use metals such as titanium (Ti), cobalt (Co), and nickel (Ni) to form silicide regions. The resulting silicides are attractive because of their ability to maintain low resistivity in narrow diffusion and polysilicon gate lines, which are used in advanced processes. [0006] However, the metal layer used to form silicide regions 141-143 may undesirably react with silicon dioxide present in dielectric sidewall spacers 105-106 during the silicide formation process. This problem, which is commonly referred to as bridging, can result in the formation of conductive (silicide or metal) residue regions 144A-144B, which can short floating gate 116 to the source and drain diffusion regions 131-132, thereby creating a leakage path for charge to drain from floating gate 116. [0007] The integrity of gate dielectric layer 115 is another concern associated with the formation of gate silicide region 143. Gate silicide region 143 can spike through floating gate 116, as illustrated by silicide spike 145 of FIG. 1. Silicide spike 145 degrades the performance of gate dielectric layer 115, and can potentially penetrate through gate dielectric layer 115 into silicon substrate 101, thereby causing a resistive short between floating gate 116 and substrate 101. In general, silicide spiking events are rare and result in minor local degradation of gate dielectric quality or a small gate dielectric leakage increase for an entire chip that contains many millions of transistors. It is, however, critical to eliminate spiking events in gate dielectric layers that are used in NVM cells, in order to preserve long floating gate charge retention for all bits in the NVM memory. Silicide spiking events are expected to get worse as gate thickness scales in advanced process generations and as industry migrates to fully-silicided (FUSI) gates. [0008] The problems introduced by NVM cell 100 are described in more detail in the following references: [1] Ken-ichi et al., "A New Leakage Mechanism of Co Silicide and Optimized Process Conditions", IEEE Transactions on Electron Devices, Vol. 4, No. 1, January 1999, pp. 117-124; and [2] S. Wolf, "Silicon Processing for the VLSI Era Volume 4--Deep-Submicron Process Technology", Lattice Press, 2002, pp. 603-634. [0009] It would therefore be desirable to have a NVM cell that can be fabricated without modifying a conventional logic process (or requiring minimal modifications to a conventional logic process), and is not susceptible to silicide spiking and silicide bridging. SUMMARY [0010] Accordingly, the present invention provides a non-volatile memory cell, which does not exhibit spiking or bridging, and is fabricated on the same substrate as conventional logic devices, in accordance with a conventional logic process. [0011] In one embodiment, the NVM cell includes an access transistor having active regions located in a semiconductor substrate, and a capacitor structure having an active region located in the semiconductor substrate, wherein the access transistor and the capacitor structure share a common polysilicon floating gate. Dielectric sidewall spacers are formed around the floating gate. [0012] A silicide-blocking dielectric structure is formed over the floating gate and the sidewall spacers prior to silicide formation. In accordance with one embodiment, portions of the active regions of the access transistor and the capacitor, which are spaced away from the sidewall spacers, are exposed by the silicide-blocking dielectric structure. Silicide regions are then simultaneously formed on the exposed portions of the active regions of the NVM cell and on the desired regions of the logic devices. [0013] In one embodiment, the silicide-blocking dielectric structure covers the entire floating gate. In another embodiment, the silicide-blocking dielectric structure can expose a section of the floating gate located over shallow trench isolation areas, such that silicide is formed over this exposed section of the floating gate. [0014] In accordance with another aspect of the invention, the silicide-blocking dielectric structure may be formed such that the silicide regions formed on the active regions of the NVM cell are separated from the edges of these active regions. This advantageously minimizes the diffusion of metallic particles from these silicide regions through the field dielectric. [0015] In another embodiment of the present invention, the silicide-blocking dielectric structure is formed entirely over the NVM cell, thereby blocking silicide formation on the active regions of the NVM cell. After silicide formation has been performed for the logic devices, the silicide-blocking dielectric structure is etched, thereby thinning or removing this structure. A pre-metal dielectric layer is formed over the resulting structure, and a contact etch is performed to expose the active regions of the NVM cell and the silicided regions of the logic devices. Thinning (or removing) the silicide-blocking dielectric structure ensures that the contact etch associated with a conventional logic process will reliably expose the active regions of the NVM cell. [0016] In another embodiment, the silicide-blocking dielectric structure is not thinned or removed. Instead, contact openings are formed in the pre-metal dielectric layer using a multi-etch procedure. In the multi-etch procedure, a partial etch is initially performed to create openings in the pre-metal dielectric layer. These openings are selectively formed only at locations overlying the active regions of the NVM cells. A conventional contact etch is then performed. This conventional contact etch extends the openings formed during the partial etch, thereby exposing the active regions of the NVM cell. The conventional contact etch also exposes the silicided regions of the logic devices. [0017] The present invention will be more fully understood in view of the following description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 is a cross-sectional view of a conventional non-volatile memory cell fabricated by a single-poly conventional logic process; [0019] FIG. 2 is a top view of a non-volatile memory cell having a PMOS access transistor and an NMOS coupling capacitor in accordance with one embodiment of the present invention; [0020] FIGS. 3A and 3B are cross-sectional views along section lines A-A and B-B, respectively, of FIG. 2. Continue reading about Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process... 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