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  Method to improve profile control and n/p loading in dual doped gate applicationsUSPTO Application #: 20070119545Title: Method to improve profile control and n/p loading in dual doped gate applications Abstract: A semiconductor processing system is provided. The semiconductor processing system includes a chamber. The chamber includes a gas inlet, a top electrode configured to strike a plasma inside the chamber, and a support for holding a substrate. A controller configured to detect a passivation starved condition during an etching operation is provided. The controller is further configured to introduce a passivation enhancing gas through the gas inlet during the etching operation in response to detecting the passivation starved condition. (end of abstract)
Agent: Martine Penilla & Gencarella, LLP - Sunnyvale, CA, US Inventors: Helene Del Puppo, Frank Lin, Chris Lee, Vahid Vahedi, Thomas A. Kamp, Alan J. Miller, Saurabh Ullal, Harmeet Singh USPTO Applicaton #: 20070119545 - Class: 156345260 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20070119545. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of and claims priority from U.S. patent application No. 10/607,612, filed on Jun. 27, 2003, which is a continuation-in-part and claims priority from application Ser. No. 10/376,227, filed on Mar. 3, 2003. The disclosures of these applications are incorporated herein by reference for all purposes. BACKGROUND OF THE INVENTION [0002] The present invention relates to an improved method for plasma etching shallow trenches and/or gate structures in the fabrication of semiconductor devices. [0003] During the manufacture of semiconductor-based products such as integrated circuits, etching and/or deposition steps may be used to build up or remove layers of material on a semiconductor substrate. A conventional etching procedure involves the use of one or more etch gases energized into a plasma state to effect plasma etching of a layer of material. Such plasma etching has been used to provide shallow trench isolation of individual transistors in an integrated circuit. After etching the trench, the trench is filled in with a dielectric material. Commonly assigned U.S. Pat. Nos. 6,218,309 and 6,287,974 disclose a shallow trench plasma etching process. [0004] In manufacture of transistors, it is conventional to etch the pattern of a photoresist layer into an underlying hard mask layer, strip the photoresist layer, and etch the pattern of the hard mask into a polysilicon layer down to a gate oxide layer. See, for example, U.S. Pat. No. 6,283,131. During polysilicon etch, e.g., reactive ion etching processes, the vertical profile is achieved by passivating the polysilicon lines laterally while etching the exposed polysilicon layer vertically. The lack of passivation during the etch process may lead to bowed or re-entrant polysilicon lines, undercut at the mask/polysilicon interface, as well as notching at the bottom of the polysilicon lines. At the same time, excess passivation may lead to tapered profiles and a foot at the base of the polysilicon lines. [0005] Additionally, for dual doped applications, where different types of doping regions co-exist on a substrate, the etching behavior of the different doped regions also differs. Consequently, this may lead to profile differences which induces critical dimension variations between the differently doped regions. Furthermore, etch rate micro-loading may also occur, thereby negatively impacting gate integrity. [0006] In view of the foregoing, there is a need for a method and apparatus to provide a proper passivation level to ensure a notch free etch profile. In addition, there is a need to mitigate profile differences and etch rate micro-loading for dual doped silicon etch processes. SUMMARY OF THE INVENTION [0007] Broadly speaking, the present invention fills these needs by introducing a passivation enhancing gas during an etching operation in order to prevent notching. It should be appreciated that the present invention can be implemented in numerous ways, including as an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below. [0008] A method of etching a shallow trench in a silicon layer includes supporting a single semiconductor substrate on a substrate support in a plasma etch chamber and plasma etching a shallow trench having a depth of less than 1 .mu.m with a width of less than 0.5 .mu.m in a silicon layer on the semiconductor substrate using an etch gas which includes a silicon containing gas. The silicon-containing gas can be used to enhance profile control and/or critical dimension control by controlled silicon deposition across the semiconductor substrate and/or provide top and/or bottom rounding. [0009] According to one embodiment, the silicon containing gas is supplied to the chamber at a first flow rate during etching of an upper region of the silicon trench layer, the silicon containing gas is supplied to the chamber at a second flow rate during etching of a middle region of the silicon trench layer, and the silicon containing gas is supplied to the chamber at a third flow rate during etching of a lower region of the silicon trench layer, the first and third flow rates being greater than the second flow rate. The first flow rate is preferably effective to provide top rounding of the trench and/or the third flow rate is preferably effective to provide bottom rounding of the trench. Preferably the upper region comprises less than 30% of the trench depth and/or the bottom region comprises less than 30% of the trench depth and/or the sidewalls of the trench are slopped at an angle of 70 to 89.degree.. In an embodiment, the first flow rate is effective to taper sidewalls of the upper region of the trench at an angle of less than 80.degree., the second flow rate is effective to taper the sidewalls of the middle region of the trench at an angle of greater than 80.degree., and the third flow rate is effective to taper sidewalls of the lower portion of the trench at an angle of less than 80.degree.. For example, the first flow rate can be effective to taper sidewalls of the upper region of the trench at an angle of 72 to 82.degree., the second flow rate can be effective to taper the sidewalls of the middle region of the trench at an angle of 82 to 88.degree., and the third flow rate can be effective to taper sidewalls of the lower portion of the trench at an angle of 72 to 82.degree.. [0010] The silicon containing gas can include SiCl.sub.4 , SiBr.sub.4 , CH.sub.3SiH.sub.3, HSiCl.sub.3, Si.sub.2H.sub.6, SiF.sub.4, SiH.sub.2Cl.sub.2, SiH.sub.4 or mixtures thereof. The etch gas further can also include a halogen-containing gas selected from Cl.sub.2, HBr, C.sub.xFy.sub.y, C.sub.xF.sub.yH.sub.z, SF.sub.6, HCl or mixtures thereof. In a preferred embodiment, the Cl.sub.2 is supplied to the chamber at a flow rate of 5 to 500 sccm and the silicon containing etch gas comprises SiCl.sub.4 supplied to the chamber at a flow rate of 1 to 100 sccm. In another embodiment, the etch gas comprises Cl.sub.2, O.sub.2, HBr, He, CF.sub.4, HCl, Ar, N.sub.2, SF.sub.6 or mixtures thereof Preferably, the etch gas is energized into a plasma state by inductively coupling radio frequency energy into the plasma chamber and/or the chamber is at a pressure of less than 100 mTorr. [0011] The silicon layer can be a portion of a single crystal silicon wafer beneath a mask such as a silicon nitride mask layer. Alternatively, the silicon layer can be an epitaxial layer, a strained silicon layer or a silicon-germanium layer on a substrate such as a single crystal silicon wafer. [0012] A method of etching a gate structure on a semiconductor substrate includes supporting a semiconductor substrate on a substrate support in a plasma etch chamber and plasma etching a gate structure in a silicon layer on the semiconductor substrate using an etch gas which includes a silicon containing gas. [0013] In the gate etch, the etch gas can include HBr, O.sub.2, Cl.sub.2, He, CF.sub.4, N.sub.2, NF.sub.3, Ar, or mixture thereof and/or the silicon containing gas can include SiCl.sub.4, SiBr.sub.4, CH.sub.3SiH.sub.3, Si.sub.2 6, SiF.sub.4, SiH.sub.2Cl.sub.2, HSiCl.sub.3, SiH.sub.4, or mixtures thereof. The gate stack preferably comprises a layer of polycrystalline silicon (polysilicon) on a silicon wafer wherein the polycrystalline silicon layer is between an underlying gate oxide and an overlying hard or soft mask layer such as a silicon nitride mask layer or photoresist. In an embodiment, an upper portion of the polysilicon layer is etched without the silicon containing gas and a lower portion of the polysilicon layer is etched while supplying the silicon containing gas at a flow rate of 1 to 100 sccm. Preferably, the etch glass is energized into a plasma state by inductively coupling radio frequency energy into the plasma chamber and/or the chamber is at a pressure of less than 100 mTorr. During the gate etch, the silicon-containing gas can be used to enhance profile control and/or critical dimension control by controlled silicon deposition across the semiconductor substrate. In a preferred process, the gate structure is etched in three steps, the etch gas including Cl.sub.2, HBr, O.sub.2 and CF.sub.4 during the first step, the etch gas including HBr and O.sub.2 during the second step and the etch gas including HBr, O.sub.2 and He during the third step, the HBr being supplied to the chamber at a higher flow rate during the second step than during the third step. [0014] In one embodiment, a method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. [0015] In another embodiment, a method for decreasing etch rate micro-loading between differently doped material of a substrate is provided. The method initiates with striking a plasma in a chamber. Then, the substrate is etched. Next, a passivation layer is formed from byproducts generated from the etching. Then, the passivation layer is enhanced. [0016] In yet another embodiment, a semiconductor processing system is provided. The semiconductor processing system includes a chamber. The chamber includes a gas inlet, a top electrode configured to strike a plasma inside the chamber, and a support for holding a substrate. A controller configured to detect a passivation starved condition during an etching operation is provided. The controller is further configured to introduce a passivation enhancing gas through the gas inlet during the etching operation in response to detecting the passivation starved condition. [0017] In still yet another embodiment, a method for enhancing a polysilicon to oxide selectivity during an etching process is provided. The method initiates with providing a substrate to be plasma etched in a chamber. Then a plasma is struck in the chamber. Next, a thin layer of a silicon containing oxide is deposited over a gate oxide as the substrate is being etched. [0018] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS [0019] The accompanying drawings, which are incorporated in and constitute part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention. [0020] FIG. 1 is a schematic illustration of a stack of layers on a silicon substrate prior to forming a shallow trench isolation feature. Continue reading... Full patent description for Method to improve profile control and n/p loading in dual doped gate applications Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method to improve profile control and n/p loading in dual doped gate applications patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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