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  Method to form etch and/or cmp stop layersUSPTO Application #: 20060089002Title: Method to form etch and/or cmp stop layers Abstract: In a DRAM fabrication process, a first oxide is provided over a transistor gate and over a substrate extending from under the gate. The deposition is non-conformal in that the oxide is thicker over the gate and over the substrate than it is on the side of the gate. A second non-conformal oxide is provided over the first non-conformal oxide. The second oxide is annealed in a boron-containing atmosphere, and the first oxide prevents boron diffusion from the second oxide into the gate and substrate. The second oxide may then serve as an etch stop, a CMP stop, or both. (end of abstract) Agent: Charles Brantley Mail Stop 525 - Boise, ID, US Inventor: Gurtej S. Sandhu USPTO Applicaton #: 20060089002 - Class: 438694000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Chemical Etching, Combined With Coating Step The Patent Description & Claims data below is from USPTO Patent Application 20060089002. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION [0001] This application is a divisional of application Ser. No. 09/531,680, filed Mar. 20, 2000. TECHNICAL FIELD [0002] The present invention relates generally to a doped non-conformal layer in a semiconductor device. More specifically, the present invention relates to a boron-doped oxide that can be used as a stopping layer for etching or chemical-mechanical planarization (CMP), among other uses. BACKGROUND OF THE INVENTION [0003] The formation of semiconductor devices (which may actually include conductive and insulative materials as well as semiconductive elements) often involves removing amounts of material included as part of the device. Occasionally, the desired result of removing material is a planarized surface. Other times, the desired result is an opening extending at least partway into the material. Examples of both results occur in the manufacture of dynamic random access memory (DRAM) devices, wherein transistor gates are formed over a semiconductor substrate. Once the gates are formed, an insulator can be deposited between and over them. The surface of this insulator is lowered to the general level of the gate top and planarized through etching or CMP. After that, a contact opening is etched through the insulator to a doped region of the semiconductor substrate that forms a transistor source or drain. This opening will subsequently be filled with conductive material, thereby allowing electrical communication with the doped substrate. [0004] This process of forming a hole within an insulation layer and filling that hole with a conductive material is generally known as a damascene process. Damascene processes offer an alternative to etching away undesired portions of a continuous conductive layer and surrounding the remaining portions with insulation. Damascene processes used at various fabrication stages provide additional examples of where material removal is desired in the context of DRAM devices. For example, initially providing the damascene insulation layer may involve CMP before the hole is formed therein, and forming the hole usually involves an etching step. [0005] During CMP or etching steps such as those described above, it is often preferable to provide some sort of CMP stop or etch stop at a location defining the extent of the removal process. Oftentimes this CMP/etch stop will be some sort of material that is more resistant if not completely immune to the CMP/etch process than is the material that is to be removed. For example, U.S. Pat. No. 5,485,035 by Lin et al. discloses using a first boron-doped oxide layer in carrying out a planarizing etch back (see Lin's FIG. 3) and a second boron-doped oxide layer to stop the via etch through an overlying insulating layer (Lin's FIG. 5). [0006] Such oxides can be deposited by growing them from a surface in an oxidizing atmosphere or by conventional deposition methods, such as chemical vapor deposition (CVD). Another method of providing oxide is a process known as Flowfill. Flowfill involves reacting silane with vaporized hydrogen peroxide. The reaction results in a gas which condenses as a liquid on a substrate cooled to about 0.degree. C. A subsequent heat treatment dries the liquid to form SiO.sub.2. [0007] As for the application of Flowfill-created oxides, prior art discloses a CMP process that stops within a Flowfill layer, although it is unclear from one particular reference whether this is a matter of properly timing the CMP or due to some property of the oxide itself. See Sabine Penka, Integration Aspects of Flowfill and Spin-on-Glass Process for Sub-0.35 .mu.m Interconnects, PROCEEDINGS OF THE IEEE 1998 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, at 271 (1998). Significantly, this reference further specifies that "Flowfill . . . need[s] to be enclosed by a base and a cap oxide." Other references further emphasize the presence of a base and cap. See, e.g., U. Hockele, et al., Flowfill-Process as a New Concept for Inter-Metal-Dielectrics, MATERIALS SCIENCE FORUM, at 235 (1998); A. Hass Bar-Ilan et al., A comparative study of sub-micron gap filling and planarization techniques, PROCEEDINGS OF THE SPIE--THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING, at 278-279 (1995); K. Beekmann et al., SUB-MICRON GAP FILL AND IN-SITU PLANARISATION USING FLOWFILL.TM. TECHNOLOGY, at 137 (1996). The base layer is an oxide provided by plasma-enhanced CVD (PECVD) and serves as an adhesion layer for the Flowfill oxide. [0008] Concerning altering the properties of Flowfill layers, U.S. Pat. No. 5,985,770, also assigned to Micron Technology Inc., discloses gas phase doping of a Flowfill layer before or during the heat treatment that ultimately solidifies the Flowfill liquid into SiO.sub.2. [0009] Given the state of the prior art in terms of CMP and etch stops, there is a constant need in the art to find a new etch stop or CMP stop and new ways of making them. Moreover, there is also a need in the art to find new applications for and modifications of the Flowfill process. SUMMARY OF THE INVENTION [0010] Accordingly, exemplary embodiments of the current invention provide a doped non-conformal oxide. In a preferred exemplary embodiment, a non-conformal oxide that resists doping is initially provided by way of a Flowfill process. Next is provided a second non-conformal oxide that is configured to accept dopant more readily. Subsequently the second oxide is annealed in an atmosphere containing boron. Alternative method embodiments include other ways of flowing at least one of the oxides. Still other alternatives address other ways of providing non-conformal oxides, such as through a high-density plasma CVD. Yet other alternative exemplary embodiments address the use of a doped non-conformal oxide as an etch stop and/or a CMP stop. BRIEF DESCRIPTION OF THE DRAWINGS [0011] FIG. 1 depicts a cross section of an in-process DRAM as known in the prior art. [0012] FIGS. 2-11 illustrate cross-sections of an in-process DRAM having undergone steps in exemplary method embodiments of the current invention. These figures also show various exemplary apparatus embodiments within the scope of the current invention. [0013] FIG. 12 illustrates a modified damascene process included as an exemplary embodiment of the current invention. [0014] FIG. 13 shows a cross-section of an in-process semiconductor device portion having undergone steps included in another exemplary embodiment of the current invention. [0015] FIG. 14 shows a cross-section of an in-process semiconductor device portion having undergone steps included in an alternative exemplary embodiment of the current invention. [0016] FIG. 15 is a cross-section of an exemplary apparatus embodiment of the current invention. [0017] FIG. 16 is a cross-section of another exemplary apparatus embodiment of the current invention. [0018] FIG. 17 is a cross-section of still another exemplary apparatus embodiment of the current invention. [0019] FIG. 18 shows a cross-section of an in-process semiconductor device portion having undergone steps included in yet another exemplary embodiment of the current invention. Continue reading... Full patent description for Method to form etch and/or cmp stop layers Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method to form etch and/or cmp stop layers patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method to form etch and/or cmp stop layers or other areas of interest. ### Previous Patent Application: Localized use of high-k dielectric for high performance capacitor structures Next Patent Application: Method for removing polymer as etching residue Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Method to form etch and/or cmp stop layers patent info. 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