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Method to eliminate pll lock-up during power up for high frequency synthesizerMethod to eliminate pll lock-up during power up for high frequency synthesizer description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060114152, Method to eliminate pll lock-up during power up for high frequency synthesizer. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. provisional patent application Ser. No. 60/627,595, filed Nov. 12, 2004, entitled "RF CHIP FOR GLOBAL POSITIONING SYSTEM RECEIVER," by Lloyd Jian-Le Jiang et al., which application is incorporated by reference herein. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to Global Positioning System (GPS) receivers, and in particular, to a method and apparatus to eliminate Phase-Lock Loop (PLL) lock-up for high frequency synthesizers used in GPS receivers. [0004] 2. Description of the Related Art [0005] The use of GPS in consumer products has become commonplace. Hand-held devices used for mountaineering, automobile navigation systems, and GPS for use with cellular telephones are just a few examples of consumer products using GPS technology. [0006] As GPS technology is being combined with these devices, the GPS chips are being placed in widely ranging applications. Some of these applications require that the GPS receiver function at low power levels, where GPS receiver manufacturers utilize techniques to shut off portions of the GPS receiver to conserve power consumption. [0007] However, when the power is turned on and off to portions of the GPS receiver, some of the components of the GPS receiver must be reset when powered up, which may place them in a condition that would provide errors for the GPS receiver. One of these components is a frequency synthesizer. At times, frequency synthesizers are placed in a condition called a "lock-up" condition, where the frequency output of the synthesizer cannot be changed as in normal operation. This prevents the frequency synthesizer from performing required functions in the GPS receiver. [0008] It can be seen, then, that there is a need in the art to provide a method and apparatus for eliminating PLL lock-up during power up in GPS receivers. SUMMARY OF THE INVENTION [0009] To minimize the limitations in the prior art, and to minimize other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method and apparatus for eliminating PLL lock-up during power up for high frequency synthesizers. [0010] A method in accordance with the present invention comprises coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop, and driving the divider with an optimum signal. [0011] Such a method further optionally forces the VCO to high amplitude and high frequency during power up, the feedback loop being a phase-locked loop, the divider being operated in a preferred region of operation. [0012] A Global Positioning System (GPS) Receiver in accordance with the present invention comprises a radio frequency section, a baseband section, and a feedback loop controlled frequency source, coupled to at least one of the baseband section and the radio frequency section, wherein the frequency source is driven to a high frequency and high amplitude when the feedback loop is at a low voltage at power-up of the GPS receiver. [0013] Such a GPS receiver further optionally includes the frequency source being a Voltage Controlled Oscillator (VCO), the feedback loop being a phase-locked loop (PLL), a divider, coupled to the frequency source within the phase-locked loop, the VCO forced to a high amplitude and high frequency when the control signal is at a low voltage, and the divider being operated in a preferred region of operation when powered-up. BRIEF DESCRIPTION OF THE DRAWINGS [0014] Referring now to the drawings in which like reference numbers represent corresponding parts throughout: [0015] FIG. 1A illustrates a block diagram of the related art; [0016] FIGS. 1B and 1C illustrate transfer functions for a VCO as performed in the related art; [0017] FIG. 2 illustrates divider operation regions of a divider of the present invention; [0018] FIG. 3A illustrates a circuit with transfer functions in accordance with the present invention; [0019] FIGS. 3B and 3C illustrate transfer functions for a VCO as performed in the present invention; [0020] FIG. 4 illustrates an application of the PLL of the present invention; and Continue reading about Method to eliminate pll lock-up during power up for high frequency synthesizer... Full patent description for Method to eliminate pll lock-up during power up for high frequency synthesizer Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method to eliminate pll lock-up during power up for high frequency synthesizer patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method to eliminate pll lock-up during power up for high frequency synthesizer or other areas of interest. ### Previous Patent Application: Gps receiver Next Patent Application: Culled satellite ephemeris information based on limiting a span of an inverted cone for locating satellite in-range determinations Industry Class: Communications: directive radio wave systems and devices (e.g., radar, radio navigation) ### FreshPatents.com Support Thank you for viewing the Method to eliminate pll lock-up during power up for high frequency synthesizer patent info. IP-related news and info Results in 0.18139 seconds Other interesting Feshpatents.com categories: Qualcomm , Schering-Plough , Schlumberger , Seagate , Siemens , Texas Instruments , 174 |
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