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Method of separating the process variation in threshold voltage and effective channel length by electrical measurements

Method of separating the process variation in threshold voltage and effective channel length by electrical measurements description/claims

The present invention relates to MOS devices and in particular to methods for separating the variance of threshold voltage with respect to dopant levels and the variance of the effective channel length.

Metal-Oxide-Silicon (MOS) devices and complementary MOS (CMOS) circuit structures have become dominant in the fabrication of circuitry for digital processing. Integrated circuits (IC) have become increasingly powerful in circuit density and circuit speed has increased. To accomplish this improvement, technologists have been able to continue this trend by device scaling and by improving materials and IC fabrication processes.

As devices have become smaller, process variations have a much greater affect on circuit performance variability and thus it is more difficult to predict the performance of an IC and thus the system in which it is intended to function.

MOS devices are basically voltage controlled current switches. The gate voltage determines how much current flows in the channel somewhat independent of the voltage across the channel from source to drain. Using the CMOS structure where there is no static power dissipation (excluding leakage) the current from an ON device is used to charge or discharge the capacitance of the gate(s) of following circuits. The drain current in a MOS device is inversely proportional to the effective channel length (Left) and directly proportional to the difference between the gate-to-source voltage (VGS) and the devices threshold voltage (VT). VGS is usually an applied voltage and VT is an intrinsic parameter which is a function of the fabrication process and its variations. To complicate matters Leff and VT are interdependent.

To accurately design a MOS fabrication process, it is necessary to isolate each parameter VT and Leff and understand what process steps are causing their variability (variance). Both of these parameters affect drain current and are difficult to directly determine as device sizes have gotten smaller, therefore, the variance of these parameters are not independently determined.

Prior art has used devices with larger channel lengths in an attempt to assure there is no Leff variability as a way of removing the interdependence of Leff and VT. However, since variance of VT due to dopant fluctuation also depends on gate area, there can be no comparison of devices with different gate areas. Others have tried to building test sites with different channel lengths but with the same gate areas. Critical dimension (CD) metrology has also be attempted but it is an expensive process.

Therefore, there is a need for a method that uses automatic testing measurements to accurately and efficiently separate the variance of threshold voltage VT with respect to dopant levels and the variance of the effective channel length Leff to allow these parameters to be controlled as scaling reduces chip device geometries.

Devices are made with a plurality of effective channel lengths Leff. Measurements are made on a statistically large number of devices at drain-to-source voltages VDS(high) and VDS(low) Since the threshold voltage VT is a function of Leff and VDS, this allows a VT versus Leff slope value λ for VDS(high) and VDS(low) to be determined experimentally; λ(H) and λ(L), respectively. Likewise, the total variance of VT may be calculated using measurements made at VDS(high) and VDS(low). Since VT is a linear function of λ times Leff over limited ranges, the variance of VT with respect to Leff may be written as the square of λ times the variance of Leff. Therefore, two equations may be written; one relating the total variance of VT at VDS(high) to the variance of VT with respect to dopant levels plus the square of λ(H) times the variance of Leff and the other relating the total variance of VT at VDS(low) to the variance of VT with respect to dopant levels plus the square of λ(L) times the variance of Leff. The total variance of VT is calculated using the measurements of VT made at VDS(high) and VDS(low). The mean or average of VT at two channels lengths and at VDS(high) and VDS(low) are calculated. These mean values of VT are used to calculate the slope values λ(H) and λ(L) at VDS(high) and VDS(low). The two equations are solved simultaneously to separately determine the variance of VT with respect to dopant levels and the variance of Leff.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which:

FIG. 1 is a curve illustrating the relationship between the threshold voltage VT and the effective channel length Leff;

FIG. 2 is curves illustrating the dependency of the curves relating VT and Leff with the drain-to-source voltage VDS; and

FIG. 3 is a flow diagram of methods steps used in embodiments of the present invention.

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