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Method of removing etch residuesRelated Patent Categories: Semiconductor Device Manufacturing: Process, Chemical Etching, Vapor Phase Etching (i.e., Dry Etching)Method of removing etch residues description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060128159, Method of removing etch residues. Brief Patent Description - Full Patent Description - Patent Application Claims
REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of application Ser. No. 10/627,151, filed Jul. 24, 2003, which is a continuation of application Ser. No. 09/141,812, filed Aug. 28, 1998 (now U.S. Pat. No. 6,613,681). FIELD OF THE INVENTION [0002] The present invention relates generally to the removal of residues during fabrication of integrated circuits. More particularly, the invention relates to the removal of residues after opening vias for contact information. BACKGROUND OF THE INVENTION [0003] During fabrication of integrated circuits, it is often necessary to construct vias to interconnect metal lines or other devices in the semiconductor. These vias, are etched through an insulating layer to expose a metal or other conductive element below. The insulating layer is typically a form of oxide, such that fluorocarbons are used to etch through the insulating layers. In plasma etch reactors, the wafer is often subjected to an electrical bias to obtain more uniform etching. Biasing the wafer also greatly increases the rate of etching. [0004] Organic residues are left in the via after the etching process. These residues can compromise the reliability of the contact to be formed within the via, and should therefore be removed. Typically, the residue is removed with an organic stripper, which simultaneously strips the resist mask. Such organic strips are expensive and difficult to dispose, however, such that oxygen plasma is more currently favored to bum off the resist and etch residue. [0005] More recently, fluorine has been added to an oxygen plasma strip, aiding the complete removal of the residue by undercutting the oxide walls. Unfortunately, the fluorine also undercuts the metal and can also laterally recess upper layers of the metal. If this lateral recessing causes a gap between the dielectric and the metal line below, filling the via with conductive material to form a contact between two layers will be incomplete, and the resulting contact will have reliability problems. [0006] U.S. Pat. No. 5,661,083 discloses reactive ion etches to clear the via walls. These etches also entail reliability issues due to metallic recessing, as well as safety problems from use of explosive mixtures and dimension control. [0007] Accordingly, there is a need for a method of effectively removing residue from etching a via. Desirably, the method should protect the via surfaces, and particularly the metal layers exposed by the via etch. SUMMARY OF THE INVENTION [0008] In accordance with one aspect of the invention, a method is provided for fabricating a conductive contact through an insulating layer in an integrated circuit. A via is first etched through the insulating layer to expose a first metal element. The via sidewall is then exposed to a vapor formed, at least in part, from ammonia. Thereafter, a conductive material is deposited into the via. [0009] In accordance with another aspect of the invention, a method is disclosed for removing etch residue from the via after the via has been etched through an insulating layer in a partially fabricated integrated circuit assembly. The etch residue is exposed -to a plasma formed from a non-explosive source of hydrogen and oxygen. In accordance with still another aspect of the invention, a method is provided for forming an integrated circuit. A patterned mask is formed from a resist layer over a dielectric layer. A via is then formed in the dielectric layer by etching through the mask. This via is cleaned by exposure to a plasma generated from ammonia. BRIEF DESCRIPTION OF THE DRAWINGS [0010] These and other aspects of the invention will be apparent to the skilled artisan from the detailed description and claims below, taking together with the attached drawings, wherein: [0011] FIG. 1 is a cross-sectional view of a partially fabricated integrated circuit, wherein a conducting layer, and a dielectric layer have been formed over a substrate; [0012] FIG. 2 illustrates the integrated circuit of FIG. 1 following deposition patterning of a mask of a layer; [0013] FIG. 3 illustrates the integrated circuit of FIG. 2 after a via has been etched through the dielectric layer, leaving residue lining the via; [0014] FIG. 4 illustrates the integrated circuit of FIG. 3 after removal of the residue and mask layer in accordance with the preferred embodiment; and [0015] FIG. 5 illustrates the integrated circuit of FIG. 4 after the via has been filled with conductive material to form a contact. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT [0016] The present invention is directed to cleaning surfaces of integrated circuits during fabrication. While illustrated in the context of removing residue from within a via following a contact etch, the skilled artisan will recognize many other applications for the methods disclosed herein. [0017] FIG. 1 shows an insulating layer 10, such as BPSG. While not shown, the insulating layer 10 is formed over a substrate in which electrical devices are formed (e.g., integrated transistors). The substrate may be a semiconductor such as silicon or gallium arsenide, or it may be an insulating layer if Silicon-On-Insulator (SOI) or a similar technology is used. For example, the insulator may be sapphire, if Silicon-On-Sapphire (SOS) is used. The term substrate is therefore meant to be inclusive of various technologies known to those skilled in the art. The insulating layer 10 thus covers and electrically isolates the electrical devices from one another and from wiring layers to be formed. [0018] A first conductive layer 12, formed over the insulating layer, may be a metal, silicide, or other suitable material. Some examples of suitable metals for forming the first conductive layer 12 include, but are not limited to, copper, gold, aluminum, silicon, and the like. Mixtures of metals are also suitable for forming a conducting layer. Some suitable mixtures of metals include, but are not limited to, aluminum alloys formed with copper and/or silicon. Some exemplary methods of depositing the conductive layer include, but are not limited to, Rapid Thermal Chemical Vapor Deposition (RTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), and Physical Vapor Deposition (PVD). Continue reading about Method of removing etch residues... Full patent description for Method of removing etch residues Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method of removing etch residues patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method of removing etch residues or other areas of interest. ### Previous Patent Application: Semiconductor structure with partially etched gate and method of fabricating the same Next Patent Application: Micro-structure manufacturing method Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Method of removing etch residues patent info. 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