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02/15/07 - USPTO Class 205 |  57 views | #20070034518 | Prev - Next | About this Page  205 rss/xml feed  monitor keywords

Method of patterning ultra-small structures

USPTO Application #: 20070034518
Title: Method of patterning ultra-small structures
Abstract: We describe a process to produce ultra-small structures of between ones of nanometers to hundreds of micrometers in size, in which the structures are compact, nonporous and exhibit smooth vertical surfaces. Such processing is accomplished with pulsed electroplating techniques using ultra-short pulses in a controlled and predictable manner.
(end of abstract)
Agent: Davidson Berquist Jackson & Gowdey LLP - Arlington, VA, US
Inventors: Jonathan Gorrell, Mark Davidson, Andres Trucco, Jean Tokarz
USPTO Applicaton #: 20070034518 - Class: 205118000 (USPTO)

Related Patent Categories: Electrolysis: Processes, Compositions Used Therein, And Methods Of Preparing The Compositions, Electrolytic Coating (process, Composition And Method Of Preparing Composition), Coating Selected Area
The Patent Description & Claims data below is from USPTO Patent Application 20070034518.
Brief Patent Description - Full Patent Description - Patent Application Claims  monitor keywords

RELATED APPLICATIONS

[0001] This application is related to U.S. patent application Ser. No. 10/917,571, filed on Aug. 13, 2004, entitled "Patterning Thin Metal Film by Dry Reactive Ion Etching," which is commonly owned at the time of filing, and the entire contents of which is incorporated herein by reference.

COPYRIGHT NOTICE

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright or mask work protection. The copyright or mask work owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright or mask work rights whatsoever.

FIELD OF THE DISCLOSURE

[0003] This disclosure relates to patterning ultra-small structures using pulsed electroplating.

INTRODUCTION

[0004] Electroplating is well known and is used in a variety of applications, including the production of microelectronics, For example, an integrated circuit can be electroplated with copper to fill structural recesses such as blind via structures.

[0005] In a basic electroplating procedure, samples are immersed in a suitable solution containing ions, typically cations, but anionic solutions are also known. An appropriate electrode is also immersed in the solution and a charge is applied that causes the deposition of metals ions from the solution onto the sample surface via an ionic reaction.

[0006] The current density, established by adjusting the electrode potential, controls the reaction rate at the sample surface. At high current density, the reaction rate becomes limited by diffusion of ions in the solution. Pulsed electroplating, also known as pulse plating, alters the current or voltage applied to the sample according to a predetermined waveform. The shape of the waveform pattern depends upon the required surface characteristics of the final plated structure.

[0007] Pulse plating can permit the use of simpler solutions containing fewer additives to achieve the plated surface. Pulse plating is well known as a method of improving coating density, ductility, hardness, electrical conductivity, wear resistance and roughness. In addition, pulse plating provides more uniform plating than other plating methods.

[0008] The production of compact, nonporous and smooth vertical surfaces is difficult with existing electroplating techniques. Porous structural morphologies produced in a controlled and predictable manner can also be advantageous to device designers.

[0009] Ultra-small structures encompass a range of structure sizes sometimes described as micro- or nano-sized. Objects with dimensions measured in ones, tens or hundreds of microns are described as micro-sized. Objects with dimensions measured in ones, tens or hundreds of nanometers or less are commonly designated nano-sized. Ultra-small hereinafter refers to structures and features ranging in size from hundreds of microns in size to ones of nanometers in size.

[0010] Catalysts, sensors, and filters represent a non-exhaustive list of examples of devices that can be fabricated or enhanced with structures of a porous morphology. The ability to create three-dimensional structures with a designed predictable structural morphology offers designers a method to realize new devices.

[0011] Ultra-small three-dimensional surface structures with sidewalls can be fabricated with coating techniques such as evaporation or sputtering. In both these techniques, a negative of the desired surface structures is created, usually using photolithographic techniques well known in the art. The patterned surface is then placed into a vacuum chamber and coated with the final material. After coating, the residual resist is removed.

[0012] However, with these techniques, patterned structures are known to cause a shadowing effect to occur during coating such that material deposition is uneven across the breadth of the patterned surface. In addition, the angles between the sidewalls created and the substrate surface often have angles other than the desired 90.degree. orientation. The ability to create smooth, dense sidewalls oriented at a 90.degree. angle relative to the substrate surface is desirable for the fabrication of a variety of ultra-small devices.

[0013] The ability to build significantly larger three-dimensional structures with smooth dense sidewalls employing the similar processing offers advantages to device designers. For example, smooth, dense sidewalls increase the efficiency of optical device function. It may also be beneficial in some microfluidic application.

[0014] Recent emphasis in the arts relates to the production of dense, smooth contiguous coatings using pulse-electroplating techniques. For example, in U.S. Patent Publication No. 20040231996A1, Web et al. describe a method of plating a copper layer onto a wafer with an integrated circuit including depressions using a pulse plating technique. In the preferred embodiment disclosed, the wafer is rotated during deposition. The rate of rotation affects the quality of layer produced. Depressions within the circuit layer are filled during the plating process.

[0015] Electroplating dendritic three-dimensional surface structures using electroplating techniques is also known. For example, U.S. Pat. No. 5,185,073, to Bindra et al., includes a description of forming dendritic surface structures using pulsed electroplating techniques. The structures produced are dense, but have angled sidewalls.

[0016] In 1995, Joo et al ("Air Cooling Of IC Chip With Novel Microchannels Monolithically Formed On Chip Front Surface," Cooling and Thermal Design of Electronic Systems (HTD-Vol. 319 & EEP-Vol. 15), International Mechanical Engineering Congress and Exposition, San Francisco, Calif. November 1995, pp. 117-121) described fabricated cooling channels using direct current electroplate of nickel. The smoothness and microstructure of the walls created was not an issue. Direct current electro-plating processing tends to produce non-uniform structures across a die or wafer.

BRIEF DESCRIPTION OF FIGURES

[0017] The invention is better understood by reading the following detailed description with reference to the accompanying drawings in which:

[0018] FIG. 1 is a schematic of a typical apparatus.

[0019] FIGS. 2(a)-2(b) are plots of typical voltage waveform according to embodiments of the present invention.

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