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Method of packing-based macro placement and semiconductor chip using the sameMethod of packing-based macro placement and semiconductor chip using the same description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070157146, Method of packing-based macro placement and semiconductor chip using the same. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001]This application claims the benefit of U.S. Provisional Application No. 60/755,954, filed on Jan. 3, 2006. BACKGROUND OF THE INVENTION [0002]1. Field of the Invention [0003]The invention relates to mixed-size design of integrated circuits and, in particular, to packing-based macro placement. [0004]2. Description of the Related Art [0005]Due to use of IP (intellectual property) modules and embedded memories, a modern VLSI chip often comprises a large number of macros. Mixed-size placement of both macros and standard cells has become more popular in different applications. As a result, many mixed-size placement algorithms are disclosed in different publications. [0006]A first type of mixed-size placement algorithm places macros and standard cells simultaneously, which typically does not consider macro orientations and requires a robust macro legalizer to remove overlaps if macros/cells are not distributed evenly. A simulated annealing based multilevel placer mPG-MS, disclosed in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference by C.-C. Chang et. al in 2003, fixes macros level by level from large macros to small macros. A min-cut based pacer Feng Shui, disclosed in Proceedings of ACM International Symposium on Physical Design by A. Khatkhate et. al in 2004, considers standard cells and macros simultaneously using a fractional cut technique, which allows horizontal cut lines to not align with row boundaries. In addition, several analytical approaches have been proposed to accomplish mixed-size placement. APlace, disclosed in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design by A. B. Kagng et. al in 2004, uses a bell-shaped potential function considering macro heights/widths based on non-linear programming to determine a global placement which evenly distributes macros/cells. mPL, disclosed in Proceedings of ACM International Symposium on Physical Design by T. Chan et. al in 2005, uses a generalized force-directed method for placement. UPlace, disclosed in Proceedings of ACM International Symposium on Physical Design by B. Yao et. al in 2005, uses quadratic programming and a discrete cosine transformation method to distribute macro/cells evenly, and a zone refinement technique for legalization is then applied. [0007]A second type combines floorplanning and placement techniques. A min-cut floorplacer Capo, disclosed in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design in 2004, is an example. The fixed-outline floorplanning is applied when necessary during min-cut placement to find allowable positions for macros. Embedded into a placement flow, floorplacement can consider macro orientations and find legal solutions more easily. [0008]A third type separates the mixed-size placement into two stages, macro placement and standard-cell placement. Macro positions are determined before standard cells are placed into the rest area. A combinational technique is disclosed in ACM Transactions on Design Automation of Electronic Systems by S. N. Adya in 2005. A standard cell placer is used to obtain an initial placement. Standard cells are clustered as several soft macros based on the initial placement, and fixed-outline floorplanning is applied to find an overlap-free macro placement. Then, macros are fixed and standard cells replaced using a standard cell placer in the remaining space. Compared with the other types, the two-stage mixed-size placement is more robust since it guarantees a feasible solution as long as an overlap-free macro placement is obtained. Furthermore, macro orientations and placement constraints, such as pre-placed macros and placement blockages, can be easily handled. BRIEF SUMMARY OF THE INVENTION [0009]An embodiment of a semiconductor chip comprises first and second groups of macros. The first and second groups of macros are respectively close packed toward first and second directions of the semiconductor chip. [0010]Another embodiment of a semiconductor chip comprises first and second groups of macros. The first and second groups of macros are respectively close packed toward first and second edges of the semiconductor chip. [0011]Another embodiment of a semiconductor chip comprises first and second groups of macros. The first and second groups of macros are respectively close packed toward first and second corners of the semiconductor chip. [0012]An embodiment of a k-level binary multi-packing tree comprises k branch nodes and k+1 packing sub-trees. Each of the k branch nodes corresponds to one level. Each of the k+1 packing sub-trees comprises a group of macros and corresponds to one of the nodes. [0013]An embodiment of a method of macro placement comprises creating a k-level binary multi-packing tree as disclosed and packing the macros of each packing sub-tree in a placement region. [0014]An embodiment of a multi-packing tree (MPT) macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format. The k-level binary multi-packing tree comprises k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros. [0015]An embodiment of a mixed-size placement design flow comprises reading initial input files in a LEF/DEF format, performing preliminary macro placement with a conventional macro placer, performing detailed macro placement with the disclosed MPT macro placer, and generating final output files in a DEF format. [0016]An embodiment of a cost function for evaluating a macro placement comprises at least one parameter of area of the macro placement, total wirelength of real nets and pseudo nets in the macro placement, total macro displacement from a preliminary macro placement, overlap length of the macro placement, and thickness of the macro placement. [0017]The invention provides a multi-packing tree (MPT)-based macro placer which places macros around a boundary of a placement region and reserves a center thereof for standard cells. The MPT macro placer is very fast for operations and packing of binary trees, with only amortized linear time needed to transform an MPT to its corresponding macro placement. As a result, a solution of macro placement is efficiently searched by simulated annealing. The packing techniques are, further, efficient and effective for area minimization, such that the MPT-base macro placer can solve mixed-size placement problems with very large macros and a large number of macros. Since macro orientations and spacing between macros are considered, the MPT-base macro placer leads to significantly shorter wirelength and less congestion than other mixed-size placers. The MPT-base macro placer can also easily function within various placement constraints, such as pre-placed blocks, corner blocks, and placement blockages. The MPT-base macro placer can be combined with state-of-the-art standard cell placers to obtain better mixed-size placement solutions based on a two-stage mixed-size placement flow. [0018]A detailed description is given in the following embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0019]The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: [0020]FIG. 1 shows a mixed size placement flow chart; [0021]FIG. 2 shows a Packing-Tree with its four types of packing; Continue reading about Method of packing-based macro placement and semiconductor chip using the same... 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