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  Method of manufacturing semiconductor device, and semiconductor deviceUSPTO Application #: 20070187735Title: Method of manufacturing semiconductor device, and semiconductor device Abstract: A first hydrogen barrier film and an intermediate layer are formed on an interlayer dielectric film. A ferroelectric capacitor is formed on the intermediate layer, and a second hydrogen barrier film is formed over the entire surface including on the upper surface and side surfaces of the ferroelectric capacitor and on the intermediate layer. Then, the second hydrogen barrier film and the intermediate layer are removed while leaving at least portions on the upper surface and side surfaces of the ferroelectric capacitor. Then, a third hydrogen barrier film is formed on the second hydrogen barrier film, on side surfaces of the second hydrogen barrier film and the intermediate layer, and on the first hydrogen barrier film. (end of abstract) Agent: Harness, Dickey & Pierce, P.L.C - Bloomfield Hills, MI, US Inventor: Katsuo Takano USPTO Applicaton #: 20070187735 - Class: 257295000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), With Ferroelectric Material Layer The Patent Description & Claims data below is from USPTO Patent Application 20070187735. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a divisional patent application of U.S. Ser. No. 11/155,031 filed Jun. 16, 2005, claiming priority to Japanese Patent Application No. 2004-181353 filed Jun. 18, 2004, both of which are hereby expressly incorporated by reference herein in their entirety. BACKGROUND [0002] 1. Technical Field [0003] The present invention relates to methods for manufacturing semiconductor devices having ferroelectric capacitors, and semiconductor devices. In particular, the present invention relates to a method for manufacturing a semiconductor device in which a ferroelectric capacitor is protected from hydrogen included in a lower layer thereof, such that electrical characteristics of the ferroelectric capacitor are difficult to deteriorate, and also relates to such a semiconductor device. [0004] 2. Related Art [0005] FIGS. 5(A) and (B) are cross-sectional views for describing a conventional method for manufacturing a semiconductor device having a ferroelectric capacitor. First, as shown in FIG. 5(A), an element isolation film 102 is formed in a silicon substrate 101 by, for example, a LOCOS method. The element isolation film 102 is open above an element region. Next, by thermally oxidizing the silicon substrate 101, a gate oxide film 103 is formed in the element region. Next, a polysilicon film is formed over the entire surface including on the gate oxide film 103, and the polysilicon film is patterned. By this, a gate electrode 104 is formed on the gate oxide film 103. Next, by using the gate electrode 104 and the element isolation film 102 as a mask, impurity ions are injected in the silicon substrate 101. By this, low concentration impurity regions 106a and 106b are formed in the silicon substrate 101. [0006] Next, a silicon oxide film is formed over the entire surface including on the gate oxide film 103, and the silicon oxide film is etched back. By this, side walls 105 are formed on side walls of the gate electrode 104. Then, by using the gate electrode 104, the sidewalls 105 and the element isolation film 102 as a mask, impurity ions are injected in the silicon substrate 101. By this, impurity regions 107a and 107b that become source and drain are formed in the silicon substrate 101. In this manner, a transistor is formed in the element region. [0007] Next, an interlayer dielectric film 108 is formed over the entire surface including on the transistor by a CVD method. In here, a material gas including hydrogen atoms, such as, SiH.sub.4, TEOS (Si(OC.sub.2H.sub.5).sub.4), or the like is used. Next, a photoresist film (not shown) is coated on the interlayer dielectric film 108, and then the photoresist film is exposed to light and developed. By this, a resist pattern is formed on the interlayer dielectric film 108. Then, by using the resist pattern as a mask, the interlayer dielectric film 108 is etched. By this, contact holes 108a and 108b respectively located above the impurity regions 107a and 107b, and a contact hole 108c located above the gate electrode 104 are formed. [0008] Then, the resist pattern is removed. Next, a Ti film and a TiN film that become a barrier metal are successively deposited by a sputter method in the contact holes 108a, 108b and 108c and on the interlayer dielectric film 108, and a tungsten (W) film is further deposited thereon. Then, the tungsten film, the TiN film and the Ti film on the interlayer dielectric film 108 are removed by a CMP (Chemical Mechanical Polishing) method or etching back. By this, W plugs 109a, 109b and 109c are embedded in the contact holes 108a, 108b and 108c, respectively. [0009] Next, a Pt film that becomes a lower electrode, a ferroelectric film and a Pt film that becomes an upper electrode are laminated in this order on the W plug 109b and the interlayer dielectric film 108. Next, a photoresist film (not shown) is formed on the Pt film that becomes an upper electrode, and the photoresist film is exposed to light and developed. By this, a resist pattern is formed on the Pt film that becomes an upper electrode. Next, by using the resist pattern as a mask, the Pt film, the ferroelectric film and the Pt film are etched. By this, a ferroelectric capacitor 110 having a lower electrode 110a, a ferroelectric film 110b and an upper electrode 110c laminated in this order on the W plug 109b is formed. Then, the resist pattern is removed. [0010] Because the ferroelectric film 110b includes oxygen, it is reduced if hydrogen, water or hydroxyl (hereafter described as hydrogen and the like) enters the ferroelectric film 110b, and its electrical characteristics deteriorate. In order to prevent this incident, a hydrogen barrier film 111 is formed on the ferroelectric capacitor 110 and the interlayer dielectric film 108. The hydrogen barrier film 111 is formed from, for example, Al oxide or Al nitride. [0011] Next, as shown in FIG. 5(B), a second interlayer dielectric film 112 is formed on the hydrogen barrier film 111 by a CVD method. In here, a material gas including hydrogen atoms, such as, SiH.sub.4, TEOS, or the like is used, but hydrogen does not reach the ferroelectric film 110b of the ferroelectric capacitor 110 because the ferroelectric capacitor 110 is covered by the hydrogen barrier film 111. For this reason, the ferroelectric film 110b does not deteriorate when the second interlayer dielectric film 112 is formed, and therefore the electrical characteristics of the ferroelectric capacitor 110 do not deteriorate. [0012] Next, a photoresist film (not shown) is coated on the second interlayer dielectric film 112, and then the photoresist film is exposed to light and developed. By this, a resist pattern is formed on the second interlayer dielectric film 112. Then, by using the resist pattern as a mask, the second interlayer dielectric film 112 and the hydrogen barrier film 111 are etched. By this, via holes 112a and 112c located above the W plugs 109a and 109c, respectively, and a via hole 112b located above the ferroelectric capacitor 110 are formed in the second interlayer dielectric film 112 and the hydrogen barrier film 111. [0013] Thereafter, the resist pattern is removed. Then, a Ti film and a TiN film that become a barrier metal are successively deposited by a sputter method in the via holes 112a-112c and on the second interlayer dielectric film 112, and a tungsten (W) film is further deposited thereon. Then, the tungsten film, the TiN film and the Ti film on the second interlayer dielectric film 112 are removed by a CMP method or etching back. By this, W plugs 113a, 113b and 113c are embedded in the via holes 112a, 112b and 112c, respectively. [0014] Next, an Al alloy film is formed over the entire surface including on the second interlayer dielectric film 112 and on the W plugs 113a-113c, and the Al alloy film is patterned. By this, Al alloy wirings 114a, 114b and 114c respectively connected to the W plugs 113a, 113b and 113c are formed. [0015] A technology similar to the above manufacturing method is described in Japanese Laid-open Patent Application 2002-176149 (FIG. 2). [0016] In the method described above, the upper surface of the ferroelectric capacitor is covered by the hydrogen barrier film. For this reason, even when hydrogen or the like is generated in a step after the ferroelectric capacitor has been formed, the hydrogen is difficult to reach the ferroelectric film of the ferroelectric capacitor. However, when the interlayer dielectric film located below the ferroelectric capacitor is heated after the ferroelectric capacitor has been formed, gas such as hydrogen or the like may be caused from the interlayer dielectric film. In this case, there is a possibility that the degassed hydrogen or the like may reach the ferroelectric capacitor, and may deteriorate the ferroelectric capacitor. Also, there is a possibility that hydrogen generated in a step after the ferroelectric capacitor has been formed may reach the ferroelectric capacitor through the interlayer dielectric film from the side of the silicon substrate. For this reason, it is desired that the ferroelectric capacitor be protected from hydrogen contained in a lower layer thereof. [0017] The present invention has been made in view of the circumstances described above, and its object is to provide a method for manufacturing a semiconductor device in which a ferroelectric capacitor is protected from hydrogen included in a lower layer thereof, such that electrical characteristics of the ferroelectric capacitor are difficult to deteriorate, and also relates to such a semiconductor device. SUMMARY [0018] To solve the problems described above, a method for manufacturing a semiconductor device, in accordance with the present invention, includes: [0019] a step of forming a first hydrogen barrier film on a dielectric film; [0020] a step of forming, on the first hydrogen barrier film, an intermediate layer composed of a film having a lower internal stress compared to the first hydrogen barrier film; [0021] a step of forming a connection hole in the first hydrogen barrier film and the intermediate layer; Continue reading... Full patent description for Method of manufacturing semiconductor device, and semiconductor device Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method of manufacturing semiconductor device, and semiconductor device patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. 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