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Method of lsi designing and a computer program for designing lsisRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or Evaluating, Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width), Timing Analysis (e.g., Delay Time, Path Delay, Latch Timing)Method of lsi designing and a computer program for designing lsis description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20050289492, Method of lsi designing and a computer program for designing lsis. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention generally relates to a timing model. More specifically, the present invention relates to a timing model of a functional block and a method of LSI (large scale semiconductor integrated circuit) designing using the timing model. [0003] 2. Background Information [0004] In the field of LSI systems and related devices, a method of turning a core functional block of an LSI into a module and recycling the functional block has become typical in recent years. This method has been pursued as a measure to shorten the length of time for designing an LSI and to improve productivity. [0005] As an example of the conventional art, Japanese Patent No. 3420195, which is hereby incorporated by reference, discloses a method of LSI designing, in particular, a method of LSI layout designing using a module. [0006] In the LSI designing using a module, logic composition, timing verification, etc. are performed using a timing model in which the timing information inside the module is incorporated. This timing information is made of input setup time, input hold time, and output delay time inside the module. In the definition of each time, clock delay time inside the module is already included. Furthermore, in the process of logic composition, pre-layout timing verification, and post-layout timing verification, the same timing model is used. [0007] In the usual LSI designing, logic composition is performed under so-called ideal clock conditions where the delay time of a clock is assumed to be zero. However, in the timing model of the module, the propagation clock conditions which contained internal clock delay time are already defined. Therefore, when designing a higher rank class using the module, the difference between the ideal clock conditions of this higher rank class and the propagation clock conditions inside the module influences the timing restrictions greatly. For this reason, it is difficult to design an LSI with a desired performance. Then, in the logic composition, it is necessary to use another timing model set as the ideal clock conditions where the clock delay time inside the module is disregarded. This is also the same in the case of pre-layout timing verification. [0008] On the other hand, in post-layout timing verification, i.e. the timing analysis performed after physical layout is completed, the timing model of the propagation clock conditions containing the clock delay time is needed. [0009] However, under the present circumstances, since the timing model which fulfills ideal clock conditions and propagation clock conditions simultaneously does not exist, it is necessary to prepare two kinds of timing models according to a design step. For this reason, the design environment tends to become complicated. Moreover, there is a possibility that design efficiency might decline. In addition, Japanese Patent No. 3420195 does not indicate any designing method of LSI for solving such a problem. [0010] In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved a method of LSI designing and a computer program for designing LSIs. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure. SUMMARY OF THE INVENTION [0011] It is therefore an object of the present invention to resolve the above-described problem, and to provide a simple and efficient timing model and a method of LSI designing which requires one kind of timing model. [0012] In accordance with a first aspect of the present invention, an LSI designing method is provided using one or more functional blocks each of which contains two or more flip flops. This LSI designing method includes the steps of: preparing a timing model which can be used under a first mode and a second mode; performing functional design of some functional elements each of which includes one or more functional blocks; with respect to the functional elements obtained by the functional design, carrying out logic composition using the timing model of the functional blocks under the first mode; with respect to the functional elements on which logic composition of the timing model of a functional block was carried out, performing a first timing analysis using the timing model under the first mode; performing layout based on the result of the logic composition and the first timing analysis; and after the layout, performing a second timing analysis using the timing model under the second mode. [0013] In accordance with a second aspect of the present invention, a computer program is provided to operate a computer to design an LSI using a timing model with respect to functional blocks. The computer program for designing an LSI includes the processes of: setting input setup time inside the functional block; setting input hold time inside the functional block; setting output delay time inside the functional block; and setting clock delay time inside the functional block independently of the other three settings. [0014] These and other objects, features, aspects, and advantages of the present invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [0015] Referring now to the attached drawings which form a part of this original disclosure: [0016] FIG. 1 is a schematic view of a functional block (module) 100 according to first, second, and third preferred embodiments of the present invention; [0017] FIG. 2 is a schematic view of a timing model according to the first embodiment of the present invention; [0018] FIG. 3 is a flow chart describing a method of LSI designing according to the first embodiment of the present invention. [0019] FIG. 4 is a schematic view of a timing model according to the second embodiment of the present invention; and [0020] FIG. 5 is a schematic view of a timing model according to the third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Continue reading about Method of lsi designing and a computer program for designing lsis... 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