| Method of forming transistor having recess channel in semiconductor memory, and structure thereof -> Monitor Keywords |
|
|
  Method of forming transistor having recess channel in semiconductor memory, and structure thereofUSPTO Application #: 20070080410Title: Method of forming transistor having recess channel in semiconductor memory, and structure thereof Abstract: Embodiments of the invention include sequentially forming a pad oxide film and a mask film on a semiconductor substrate, and then forming an opening for partially exposing the pad oxide film. An undercut region is formed using the mask film as an etch mask, exposing a partial surface of the substrate. A spacer is formed surrounding both sidewalls of the mask film, and a recess is formed in the substrate. A gate oxide film, a gate electrode, a gate insulation film, a gate spacer, and source and drain regions are also formed. A resultant transistor structure has a small open critical dimension that improves process margin and provides uniformity to the recess depth, and removes a requirement that a bottom critical dimension of a subsequently formed self-aligned contact should be small. Degradation of the gate oxide film and increases in leakage current may also be prevented. (end of abstract) Agent: Marger Johnson & Mccollom, P.C. - Portland, OR, US Inventor: Ji-Young KIM USPTO Applicaton #: 20070080410 - Class: 257401000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Field Effect Transistor In Integrated Circuit, With Specified Physical Layout (e.g., Ring Gate, Source/drain Regions Shared Between Plural Fets, Plural Sections Connected In Parallel To Form Power Mosfet) The Patent Description & Claims data below is from USPTO Patent Application 20070080410. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a Divisional of U.S. patent application Ser. No. 10/867,845, filed on Jun. 14, 2004, now pending, which claims priority from Korean Patent Application No. 2003-39164, filed on Jun. 17, 2003, the contents of which are hereby incorporated by reference for all purposes. BACKGROUND OF THE INVENTION [0002] 1. Technical Field Of The Invention [0003] This disclosure relates to transistor manufacturing for a semiconductor memory, and more particularly, to a transistor having a recess channel and a method for forming the same. [0004] 2. Description of the Related Art [0005] A MOS transistor is generally constructed of gate, drain and source regions. A gradually increasing integration density in semiconductor devices requires the continued miniaturization of transistors, but there is a limitation in that a junction depth of a source and drain region can't become exceedingly shallow. That is, the gradual reduction of the length of channel causes the depletion region of the source and drain to invade the interior of channel, reducing the effective length of the channel along with the threshold voltage. A short channel effect is thus generated, and gate control function in the MOS transistor is lost. The shortened channel length causes a high electric field in the semiconductor device, which generates a hot carrier. The hot carrier brings about collision ionization and the hot carrier thus invades an oxide film. The oxide film is thus degraded. [0006] In order to prevent these short channel effects, a thickness of a gate insulation film should be reduced, and a channel between the source and drain, namely, a maximum width of the depletion region provided under the gate should be reduced, and a density of dopant in the semiconductor substrate should be reduced. [0007] In order to prevent the short channel effect, conventional methods have attempted to ion implant a dopant of opposite conductivity type into a lower part of the channel region, together with the shallow junction. Furthermore, in order to prevent the hot carrier effect, most conventional transistor manufacturing processes employ a lightly doped drain (LDD) structure, which forms a buffering region of a low density implantation between the gate region and the drain region, which have a high density implantation. However, since the channel length is continuously shortened by tendency to increase the integration density of the semiconductor device, the transistor of the LDD structure has the short channel and hot carrier phenomena, too. Furthermore, the dopants in the source and drain regions are diffused to a side thereof, by a punchthrough effect, during operation of the transistor. [0008] In order to solve these problems, a transistor structure has been proposed that has a gate formed in a recess channel that is formed in the semiconductor substrate. The recess is formed in a region where a channel of the transistor would be formed, increasing an effective channel length and improving the punchthrough resistance of the source and the drain regions. The recess actually widens a distance between the source and the drain, enhancing a high-integration density of the semiconductor device. [0009] FIGS. 1 to 7 are cross-sectional views illustrating a sequential manufacturing process for a transistor having a recess channel according to the conventional art. [0010] With reference to FIG. 1, a low density doping layer 18 is formed through an ion implantation on a semiconductor substrate 12 on which a device separation film 14 is formed, and a channel adjusting dopant layer 16 is formed to prevent punchthrough. On the semiconductor substrate 12 on which the low density doping layer 18 and the channel adjusting dopant layer 16 were formed, an oxide film 20 and a mask film 22 are formed. [0011] In FIG. 2, an opening 23 having a predetermined pattern is formed in the mask film 22. [0012] An open critical dimension (CD) in an upper part of the opening 23 is about 90 nm, and a CD in a lower part of the opening 23 is about 50 nm. [0013] In FIG. 3, the semiconductor substrate 12 and the oxide film 20 exposed in the lower part of the opening 23 are etched by using the mask film 22 as an etch mask, to thus form a recess 24. [0014] A process of forming the recess 24 includes a break-through (BT) process of removing the oxide film 20 and a process of forming the recess 24. [0015] FIG. 4 illustrates the semiconductor substrate 12 having the recess 24 formed after a chemical dry etching (CDE) process is performed to remove the mask film 22. [0016] The recess 24 has a generally large open CD and the upper edge of the recess 24 is formed as a pointed shape. [0017] In FIG. 5, the oxide film 20 remaining on the semiconductor substrate 12 is removed and this is passed through a thermal oxide process, then a gate oxide film 26 is formed on an overall face of the semiconductor substrate 12 including the recess 24. [0018] In FIG. 6, a gate stack 33 containing a gate electrode 28 formed of polysilicon, a metal silicide layer 30, and a gate insulation film 32, is formed on the semiconductor substrate 12 having the gate oxide film 26. [0019] The CD of the gate stack 33 is about 60 nm, smaller than the upper open CD of the recess, to be entered inside the recess 24. [0020] In FIG. 7, gate spacers 34 are formed on either side of the gate stacks 33. [0021] Source and drain regions are formed by implanting a high-density doping ion into the semiconductor substrate 12 having the gate spacer. A series of these processes completes the conventional transistor having the recess channel. [0022] This method of forming the transistor according to the conventional art exhibits the following problems. Continue reading... Full patent description for Method of forming transistor having recess channel in semiconductor memory, and structure thereof Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method of forming transistor having recess channel in semiconductor memory, and structure thereof patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method of forming transistor having recess channel in semiconductor memory, and structure thereof or other areas of interest. ### Previous Patent Application: Method for forming a silicidated contact Next Patent Application: Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate mosfet device and method of manufacture thereof Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Method of forming transistor having recess channel in semiconductor memory, and structure thereof patent info. IP-related news and info Results in 1.72332 seconds Other interesting Feshpatents.com categories: Accenture , Agouron Pharmaceuticals , Amgen , AT&T , Bausch & Lomb , Callaway Golf |
||
