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  Method of forming metal/high-k gate stacks with high mobilityUSPTO Application #: 20060289903Title: Method of forming metal/high-k gate stacks with high mobility Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater. (end of abstract) Agent: Scully Scott Murphy & Presser, PC - Garden City, NY, US Inventors: Wanda Andreoni, Alessandro C. Callegari, Eduard A. Cartier, Alessandro Curioni, Christopher P. D'Emic, Evgeni Gousev, Michael A. Gribelyuk, Paul C. Jamison, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Carlo A. Pignedoli, Joseph F. Shepard, Sufi Zafar USPTO Applicaton #: 20060289903 - Class: 257287000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Junction Field Effect Transistor (unipolar Transistor), With Multiple Channels Or Channel Segments Connected In Parallel, Or With Channel Much Wider Than Length Between Source And Drain (e.g., Power Jfet) The Patent Description & Claims data below is from USPTO Patent Application 20060289903. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a divisional of U.S. application Ser. No. 10/873,733, filed Jun. 22, 2004. FIELD OF THE INVENTION [0002] The present invention relates to a semiconductor structure and more particularly to a gate stack structure that includes an interfacial layer comprising atoms of at least silicon and oxygen and an overlaying high-k gate dielectric. The term "high-k" is used throughout the present application to denote a dielectric material that has a dielectric constant, as measured in a vacuum, that is greater than SiO.sub.2. The gate stack structure of the present invention, which is annealed at a temperature of about 800.degree. C. or above, has improved electron mobility and low interfacial charge density as compared to a conventional gate stack structure. Additionally, the present invention also relates to a method of forming the inventive gate stack structure. Moreover, the present invention provides a semiconductor device, i.e., metal oxide semiconductor field effect transistor (MOSFET), that includes at least the inventive gate stack structure. BACKGROUND OF THE INVENTION [0003] In the quest for improved performance, electronic circuits are becoming denser and the devices therein are becoming smaller. For example, the most common dielectric in metal oxide field effect transistors (MOSFETs) has been SiO.sub.2. However as the thickness of SiO.sub.2 approaches 15 .ANG., substantial problems appear, including, for example, leakage currents through the gate dielectric, concerns about the long-term dielectric reliability, and the difficulty in manufacturing and thickness control. [0004] One solution to the above problem is to use thick (greater than 20 .ANG.) films of materials, such as hafnium oxide (HfO.sub.2), that have a dielectric constant that is larger than SiO.sub.2. Thus, the physical thickness of the gate dielectric can be large, while the electrical equivalent thickness relative to SiO.sub.2 films can be scaled. [0005] Introduction of high-k dielectrics, such as HfO.sub.2, ZrO.sub.2 or Al.sub.2O.sub.3, in gate stacks has proven to reduce leakage current by several orders of magnitude. Such leakage current reduction has enabled the fabrication of complementary metal oxide semiconductor (CMOS) devices with lower power consumption. Unfortunately, other problems have arisen from utilizing high-k dielectrics in CMOS devices including difficulty of passivating the underlying silicon, the introduction of unwanted charges in the gate stack that produce large flat band voltage shifts, large threshold voltage shifts, significant charge trapping and low electron mobility devices. [0006] Indeed, it has been reported that the electron mobilities of metal gate electrode/high-k gate dielectric stacks formed on a silicon substrate are severely degraded when compared with conventional poysilicon/SiO.sub.2 gate stacks. See, for example, Callegari, et al., Int. Conf SSDM, September 16-18, Tokyo, Japan 2003. Despite having degraded electron mobilities, the use of high-k gate dielectrics in the next generation of very large scale integrated (VLSI) circuits is necessary to reduce leakage currents in CMOS devices. Remote phonon scattering or remote charge scattering have been suggested to explain mobility degradation for nFETs. See M. V. Fischetti, et al., "Effective Electron Mobility in Si Inversion Layers in MOS systems with a High-k Insulator: The Role of Remote Phonon Scattering", J. Appl. Phys. 90, 4587 (2001) and M. Hiratani, et al. JJAP Vol. 41, p. 4521 (2002). [0007] In high-k dielectrics, such as HfO.sub.2, a metal-oxygen bond is easily polarizable under an external electric field, which results in highly undesirable scattering of channel mobile charges by remote phonons present in the high-k material. As the result, the MOS device drive current can be substantially reduced by the presence of high-k materials as the gate insulator. Several existing solutions are directed to the reduction of the scattering problem. In one known solution, a layer of silicon oxide or silicon oxynitride is disposed between the channel located within the Si substrate and the high-k gate dielectric. Some of the remote phonon scattering is reduced using these so-called interlayers because the high-k gate dielectric is positioned further away from the channel. [0008] Although prior art gate stack structures (including a conventional interlayer and high-k dielectric) have reduced remote phonon scattering, they still do not achieve the electron mobility of MOS devices that contain SiO.sub.2 as the gate dielectric. Hence, there is still a need for providing a MOS device stack, which contains a high-k gate dielectric and a metal gate, that has improved electron mobility that is substantially equivalent to conventional SiO.sub.2-containing MOS devices. SUMMARY OF THE INVENTION [0009] The present invention provides a gate stack structure that has improved electron mobility as compared with conventional metal/high-k gate stacks. Specifically, the gate stack structure of the present invention includes an interfacial layer comprising atoms of at least Si and O and having a dielectric constant greater than SiO.sub.2 and an overlaying high-k gate dielectric, said gate stack structure having an interface state density, as measured by charge pumping, of about 8.times.10.sup.10 charges/cm.sup.2 or less, a peak mobility of about 250 cm.sup.2/V-s or greater, and substantially no mobility degradation at about 6.0.times.10.sup.12 inversion charges/cm.sup.2 or greater. The term "substantially no mobility degradation is used throughout the present invention to denote that the mobility at the said inversion charge level does not drop beneath the universal curve provided in FIG. 3 of the present application. No mobility degradation in the inventive gate stack structure occurs at about 8.0.times.10.sup.12 inversion charges/cm.sup.2 or greater. [0010] The term "interface state density" denotes interface states located at the Si/interfacial layer interface and/or at the high-k gate dielectric/interfacial layer interface. The term "peak mobility" denotes maximum electron/hole mobility in the MOSFET channel, and the term "inversion charge" denotes the mobile charges in the MOSFET channel. The interfacial layer may contain N atoms as long as the concentration of the N atoms is about 1E15 atoms/cm.sup.2 or less. More typically, the N atoms are present in the interfacial layer in a concentration from about 1E14 to about 3E15 atoms/cm.sup.2. Above the broad nitrogen concentration range stated herein, degradation of the peak mobility is typically observed. The interfacial layer may also include materials from the overlaying high-k gate dielectric including, for example, metal, oxide, silicate or a mixture thereof. [0011] In addition to the gate stack structure, the present invention also provides a semiconductor device, i.e., MOSFET, that includes at least the gate stack structure of the present invention. Specifically, the semiconductor device of the present invention comprises a semiconductor substrate, a gate stack structure comprising an overlaying high-k gate dielectric and an interfacial layer comprising at least atoms of Si and O and having a dielectric constant greater than SiO.sub.2 located on a surface of said semiconductor substrate; and a gate conductor located atop the gate stack structure, wherein said gate stack structure has an interface state density, as measured by charge pumping, of about 8.times.10.sup.10 charges/cm.sup.2 or less, a peak mobility of about 250 cm.sup.2/V-s or greater and substantially no mobility degradation at about 6.0.times.10.sup.12 inversion charges/cm.sup.2 or greater. [0012] The gate stack structure of the present invention exhibits substantially no degradation in peak mobility at electron fields of about 0.8 MV/cm.sup.2 or greater. [0013] In some embodiments of the present invention, an optional diffusion barrier can be present between different gate conductor materials. The semiconductor device of the present invention may comprise a self-aligned MOSFET or a non-self-aligned MOSFET. [0014] In addition to the above, the present invention also provides a method of fabricating the inventive gate stack structure which has the properties mentioned above. Specifically, and in broad terms, the gate stack structure of the present invention is formed by the following steps that include: [0015] providing a stack including an interlayer comprising at least atoms of Si and O and an overlying high-k gate dielectric; and [0016] annealing said stack at a temperature of about 800.degree. C. or greater so to provide a gate stack structure having an interface state density, as measured by charge pumping, of about 8.times.10.sup.10 charges/cm.sup.2 or less, a peak mobility of about 250 cm.sup.2/V-s or greater and no substantially mobility degradation at about 6.0.times.10.sup.12 inversion charges/cm.sup.2 or greater. [0017] During the annealing step, the interlayer is regrown and some intermixing with the overlaying high-k gate dielectric occurs resulting in the formation of the interfacial layer of the inventive gate stack structure. The interfacial layer of the present invention is thus different from conventional interlayers since it undergoes regrowth and intermixing which occur during the high temperature annealing step of the present invention. [0018] The method described above can be integrated within conventional self-aligned or non-self-aligned CMOS processing steps to provide at least one MOFFET device. BRIEF DESCRIPTION OF THE DRAWINGS [0019] FIG. 1 is a pictorial representation (though a cross sectional view) illustrating the inventive gate stack structure positioned between a semiconductor substrate and a gate conductor. Continue reading... Full patent description for Method of forming metal/high-k gate stacks with high mobility Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method of forming metal/high-k gate stacks with high mobility patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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