| Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using soi wafers -> Monitor Keywords |
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Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using soi wafersRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Device Or Circuit Responsive To Nonelectrical Signal, Responsive To Electromagnetic Radiation, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged SemiconductorMethod of forming an implantable electronic device chip level hermetic and biocompatible electronics package using soi wafers description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080090322, Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using soi wafers. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of U.S. application Ser. No. 10/360,988, "Chip Level Hermetic and Biocompatible Electronics Package Using SOI Wafers", filed Feb. 7, 2003, the disclosure of which is incorporated herein by reference, which claims the benefit of U.S. Provisional Application No. 60/440,806, "Chip Level Hermetic and Biocompatible Electronics Package Using SOI Wafers", filed Jan. 17, 2003, the disclosure of which is incorporated herein by reference. FIELD OF THE INVENTION [0002] This invention relates to a hermetic integrated circuit and a method of making an integrated electronic circuit by utilizing silicon-on-insulator (SOI) techniques. BACKGROUND OF THE INVENTION [0003] This invention relates to electrically insulating thin film processes that are hermetic and that are used to encapsulate integrated circuits (ICs) for the purpose of forming a protective package for an electronic circuit, where the ICs are applicable to devices that are implanted in living tissue, such as neural prostheses or retinal electrode arrays. The package may have electrical feedthroughs to connect electrically to the outside environment. The electric circuit may interface with the outside environment optically (for example, infrared or laser) or via electromagnetic means, such as radio frequency (RF) and thus it may not need an exposed feedthrough. Additionally, the hermetic film may be made selectively electrically conductive in certain regions to facilitate signal transmission or power transmission. [0004] The main drawback to thin film packaging of electronic circuits that are implanted in living tissue is that the process is typically three-dimensional since the entire IC needs to be packaged (encapsulated in a thin film). This results in long deposition times that add cost and that could exceed the thermal budget of the electronic circuits, thereby destroying the device. The invention describes a device and means for reducing the required deposition process time by allowing an equivalent package to be constructed in a two-dimensional deposition that covers several chips at the same time at the wafer level. SUMMARY OF THE INVENTION [0005] In accordance with a preferred embodiment of this invention, the apparatus of the instant invention is a hermetic and biocompatible electronics package that is made by applying silicon-on-insulator (SOI) technology and thin film deposition technology to enable large-scale production of individual integrated circuits for electronic packages that may be implantable in living tissue. [0006] The SOI wafer is diced partially through its thickness. The spaces between the chips, die, or reticules are scored or semi-diced by one of several known means, in order to produce three-dimensional streets. The depth of these three-dimensional streets passes completely through the silicon layer and partially through the insulating layer. The three-dimensional streets are then coated along with the silicon layer to yield a hermetic electronics package that is suitable for implantation in living tissue. [0007] In accordance with an alternative embodiment, the thin silicon layer may be transparent to light, thus allowing light to strike a photodetector on the surface away from the light source. This may have application in neural prostheses or retinal electrode arrays, for example, where light passes through the integrated circuit, strikes a photodetector, which in turn stimulates the retina to enable vision in a non-functioning eye. In this case, it passes through the insulator then through the silicon/integrated circuit layer. [0008] A further embodiment places discrete electronic circuit components in the street area of the integrated circuit. The discrete component is then coated and thus part of the hermetically sealed, implantable electronics package. [0009] The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings. OBJECTS OF THE INVENTION [0010] It is an object of the invention to produce a hermetically sealed integrated circuit using silicon-on-insulator technology and thin film deposition technology. [0011] It is an object of the invention to produce a light transparent thin-layered integrated circuit chip using silicon-on-insulator techniques. [0012] It is an object of the invention to produce a discrete integrated circuit that has discrete electronic components hermetically protected wherein select components are located in the street area of the integrated circuit. [0013] Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawing. BRIEF DESCRIPTION OF THE DRAWINGS [0014] FIG. 1 illustrates a cross sectional side view of the silicon-on-insulator chip assembly. [0015] FIG. 2 depicts a cross sectional side view of the silicon-on-insulator chip assembly showing the insulating thin film. [0016] FIG. 3 depicts a cross sectional side view of a single silicon-on-insulator chip. [0017] FIG. 4 illustrates a cross-sectional side view of a light transparent insulator with a photoelectric cell. [0018] FIG. 5 depicts a hermetically coated silicon-on-insulator IC with a discrete component. Continue reading about Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using soi wafers... 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