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Method of forming an electrical contactRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive MaterialMethod of forming an electrical contact description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070059915, Method of forming an electrical contact. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of application Ser. No. 11/011,420, filed Dec. 13, 2004, pending, which is a continuation of application Ser. No. 10/423,239, filed Apr. 25, 2003, now U.S. Pat. No. 6,831,472, issued Dec. 14, 2004, which is a divisional of application Ser. No. 09/387,987, filed Sep. 1, 1999, now U.S. Pat. No. 6,556,030, issued Apr. 29, 2003. BACKGROUND OF THE INVENTION [0002] 1. Technical Field [0003] The present invention relates generally to a device and method for providing electrical communication with a packaged integrated circuit device. More specifically, the present invention concerns a silicon interconnect and a method for fabricating a silicon interconnect for a Land Grid Array package. [0004] 2. State of the Art [0005] In testing a semiconductor die, it is often useful to establish an electrical connection between the test equipment and the circuitry of a die. Testing may be performed on an unpackaged die that has been singulated from a semiconductor wafer, on a section of dice that is still part of the wafer, or on all of the dice on a wafer. In order to test a singular die, a partial wafer, or a full wafer, it may be beneficial to house the die structure in a temporary package such as a socket. The socket is configured to attach to a board which, in turn, is coupled to the test circuitry. One way to establish electrical communication between the die's bond pads and the socket is through the use of an interconnect. The interconnect is often made of silicon or some other etchable material, which may be coated with a conductive material to aid in electrical communication. The use of etchable materials such as silicon allows for the use of semiconductor fabrication techniques to form electrical contact members from a silicon substrate. Such techniques enable formation of electrical contact members at a pitch matching that of the die's bond pads. Silicon interconnects accommodate dice in other ways as well. For example, it is noteworthy that a die's bond pads are often made of aluminum. Given the temperatures associated with certain tests, it is important that the outermost coating of the interconnect be of some material other than aluminum; otherwise, the interconnect will permanently weld to the die during testing. Thus, it is taught in the art to coat a silicon interconnect with a material that is different from the material it will temporarily contact. Moreover, aluminum oxidizes relatively easily and, as a result, a die's aluminum bond pads are often covered with a thin film of nonconductive aluminum oxide. An interconnect must penetrate this oxide to reach the conductive aluminum of the bond pad in order to establish good electrical contact. To achieve this, it is taught to include fabrication steps that provide penetrating elements, such as blades, on the top of each interconnect contact. Steps that provide such elements are addressed in more detail in U.S. Pat. Nos. 5,326,428 and 5,419,807. These elements, while considered to be an improvement over flat contacts to a die's bond pads (see, for example, U.S. Pat. No. 5,607,818), necessarily cause damage to the bond pads and may shorten their useful life. Moreover, there is a risk that the elements will break off of the interconnect's contact. [0006] These fabrication steps result in an interconnect that is configured to be inserted into the socket, receive a die's bond pads therein, and connect them to electrical terminals of the socket. Given the material of the interconnect and its placement in the package, such an interconnect is often referred to as a "silicon insert." The die is placed in the socket so that the die's bond pads are aligned with the interconnect's contact members; the socket is attached to the board; the board is coupled to the test circuitry; and testing commences. [0007] After testing, the die may be removed from the socket. The interconnect may be removed as well, perhaps to be replaced by another interconnect having a different arrangement of contact members for another die. Dice that do not pass testing may be discarded, while those that do pass may undergo further processing, such as a burn-in process, and packaging. [0008] Concerning the packaging of a die, there are varying degrees and types of packaging that a die may undergo. For example, a die may be configured as a "flip chip," wherein conductive material such as solder balls is attached directly to the bond pads or electrical traces formed in the surface of the die; the die is then "flipped," or mounted face down, so that the solder balls may connect with contact members of another device, such as a carrier substrate. Another example is a "chip scale package," which includes a die along with one or more minimal package elements, such as an encapsulating material in the form of a thin protective coating formed of glass or other materials. Such a coating may be bonded at least to the active surface of the die and edges thereof and sometimes to the sides and back side of the die as well. In addition, solder balls may be attached to electrical traces in the surface of the die or directly to the die's bond pads through openings in the encapsulating material in order to provide the aforementioned "flip chip" configuration. A Ball Grid Array (BGA) package serves as yet another example that involves even more packaging: the die is wire bonded to a substrate and encapsulated, and an array of solder balls on one side of the substrate is bonded to electrical traces leading through the substrate to the die. Alternatively, the package may comprise a Land Grid Array (LGA), which is similar to a BGA, except that flat contact pads--or lands--serve as external electrical communication nodes on the substrate instead of solder balls. Similarly, if an array of pins serves as the external electrical communication nodes for the package, such a package is known as a Pin Grid Array (PGA). [0009] Other types of packages known in the art include dual in-line packages (DIP), wherein the leads extending from the package define two lines. Zigzag in-line packages (ZIP) have a line of leads, wherein every other lead extends into one of two planes (see U.S. Pat. No. 4,790,779). Leadless chip carrier (LCC) packages use sockets or conductive pads in place of leads and are configured to directly connect to a circuit board (see U.S. Pat. No. 5,375,320). Small outline packages (SOP) and thin small outline packages (TSOP) use a plastic ring around the package to contact the far end of the leads extending straight from two opposing edges of the package. The plastic ring can be removed after testing, and the leads may then be bent as needed. Quad flat pack (QFP) packages are similar to the SOPs in that a plastic ring surrounds the package and contacts the far end of the leads. In the QFP, however, the leads extend from four sides of the package (see also FIG. 6 of U.S. Pat. No. 5,903,443). Small outline j-bend (SOJ) packages use leads bent in a "j" shape, which allows for resiliency once the packages are attached to a circuit board. [0010] As for testing these packaged dice, current methods of doing so also have problems. For example, testing LGA packages involves contacting the lands of the LGA with pins that have been stamped from a metal sheet. Each pin is placed within a hole that is one of an array of holes found within a plastic mold. This mold keeps an array of pins aligned with the package's array of lands. Test equipment may then access the lands through these pins. Unfortunately, there are several problems with using such pins. First, as the overall size of packages becomes smaller, the area of the lands decreases, as does the space between the lands. It is difficult for the stamped pins/plastic mold formation process to match the rate at which die packages are shrinking. In addition, using such pins often results in high inductance, thereby interfering with testing. Moreover, as with the silicon interconnects and the die bond pads, there exists the risk of a scrubbing action of the pins against the lands, which could damage both the pins and the lands. [0011] Thus, there is a need in the art for improved testing structures and methods, including a need for improved temporary packaging for testing dice that have already undergone some degree of packaging. Included within this need is the desire to establish electrical communication between an interconnect and a related packaged die. Further, there is a more general need for improved electrical communication with a die, whether such communication is with a die as part of a permanently packaged part or a temporarily packaged part, or whether such communication is for test or non-test purposes. BRIEF SUMMARY OF THE INVENTION [0012] Accordingly, the current invention provides an electrical connector and a method of forming it. Many exemplary embodiments of the current invention apply semiconductor fabrication techniques to an interconnect for a packaged part while reducing, if not eliminating, the problems attendant with prior silicon interconnects and prior interconnects for packaged parts. Such embodiments involve forming silicon interconnects having a contact surface that is complementary to the electrical contact surface of the packaged part to be tested. In some embodiments, such as those configured to contact LGA packages, the interconnect's contact surface is planar and parallel to the packaged part's contact surface. In more general embodiments, the interconnect's contacts are non-invasive or non-penetrating with respect to the electrical contacts of the packaged part. Some of these embodiments may be described as defining "male-female" configurations between the interconnect's contact surface and that of the packaged part. [0013] An exemplary method of fabricating interconnects such as the ones described above involve defining a projection or protrusion from a substrate; providing a passivation/insulation layer over the substrate, including the projection; providing at least one seed layer over the passivation/insulation layer; providing at least one metal layer over the seed layer; and simultaneously patterning the metal layer and seed layer. In a preferred embodiment, the metal layer of the interconnect is the same metal as the packaged part's contact points. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS [0014] FIG. 1 depicts two in-process electrical connectors having undergone processes known in the prior art. [0015] FIG. 2 illustrates two in-process electrical connectors having undergone a step included within an exemplary embodiment of the current invention. [0016] FIG. 3 illustrates two in-process electrical connectors having undergone another step included within an exemplary embodiment of the current invention. [0017] FIG. 4 illustrates two in-process electrical connectors having undergone yet another step included within an exemplary embodiment of the current invention, as well as a cross-sectional view of a first exemplary apparatus embodiment of the current invention. [0018] FIG. 5 illustrates a top-down view of the first exemplary apparatus embodiment of the current invention. [0019] FIG. 6 illustrates a top-down view of a second exemplary apparatus embodiment of the current invention. [0020] FIG. 7 illustrates a top-down view of a third exemplary apparatus embodiment of the current invention. Continue reading about Method of forming an electrical contact... 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