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Method of fabricating semiconductor devices and method of adjusting lattice distance in device channelRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.)Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060228843, Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor process, and more particularly to a method of fabricating a semiconductor device and a method of adjusting a lattice distance in the device channel region. [0003] 2. Description of the Related Art [0004] In the early days, a metal-oxide-semiconductor (MOS) device is composed of a metal gate electrode, a gate dielectric layer, and a semiconductor substrate. Because the adhesion of most metals to silicon is unsatisfactory, currently, the material of the gate electrode is polysilicon. The application of a polysilicon gate electrode, however, incurs other issues. For example, the device performance decays due to the high resistance of the polysilicon. Accordingly, with the present technology, after forming the device, a salicide process is performed to form metal silicide on the gate electrode and the source/drain regions to reduce the resistance of the device. [0005] In another aspect, a chip usually comprises a device area and a peripheral circuit area, wherein, devices in the device area include, for example, memory devices, and electro-static discharge (ESD) protection circuits. Devices in the peripheral circuit area comprise, for example, logic devices. The devices in the device area require high resistances than those in the peripheral circuit area. During the salicide process above, a block layer is used to cover the area on which the metal silicide is not going to be formed. Because the area covered by the block layer does not require additional film layer to prevent the formation of metal silicide, the block layer is also called a self-aligned salicide block layer (SAB) layer. [0006] FIGS. 1A-1E are schematic cross sectional views showing the progression of a prior art method of fabricating a semiconductor device. Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 includes a device area 102, and a peripheral circuit area 104. Gate structures 106 and 108 are formed over the substrate 100 of the device area 102 and the peripheral circuit area 104, respectively. Lightly-doped regions 110 and 112 are formed in the substrate 100 and adjacent to the sidewalls of the gate structures 106 and 108. [0007] Referring to FIG. 1B, after forming spacers 114 on the sidewalls of the gate structures 106 and 108, the source regions 116a and 118a, and the drain regions 116b and 118b are formed in the substrate 100 and adjacent to the spacers 114. An anneal process 120 is performed to the source regions 116a and 118a, and the drain regions 116b and 118b. [0008] Referring to FIG. 1C, an SAB layer 122 is formed over the substrate 100, covering the gate structures 106 and 108, and the exposed surface of the substrate 100. [0009] Referring to FIG. 1D, the SAB layer 122 in the peripheral circuit area 104 is removed, and the SAB layer 122a in the device area 102 is reserved. A metal layer 124 is then formed over the substrate 100, covering the SAB layer 122a, the gate electrode 108, and the exposed surface of the substrate 100. [0010] Referring to FIG. 1E, a thermal process is performed so that a portion of the metal layer 124 reacts with silicon under the metal layer 124 to form a metal silicide layer 126. The unreacted metal layer 124 is then removed. [0011] In the process described above, the formation of the metal silicide layer can solve the problem of high resistance of the device. However, when the size of the device shrinks, the lattice distance in the channel region 128 seriously affects the electron mobility. The lattice distance becomes an essential factor in determining the device performance. SUMMARY OF THE INVENTION [0012] Accordingly, the present invention is directed to a method of fabricating a semiconductor device to improve device performance. [0013] The present invention is also directed to a method of adjusting a lattice distance of a device channel region to enhance electron mobility in the channel region. [0014] The present invention provides a method of fabricating a semiconductor device. The method forms a plurality of gate structures over a substrate. A source region and a drain region corresponding to each gate structure are formed in the substrate and adjacent to the sidewalls of each of the gate structures. A self-aligned salicide block (SAB) layer is formed to cover the gate structures and an exposed surface of the substrate. An anneal process is performed. During the anneal process, the SAB layer creates a tension stress so that the substrate under the gate structures is subject to the tension stress. A self-aligned salicide process is performed. [0015] According to a method of fabricating a semiconductor device of a preferred embodiment of the present invention, the material of the SAB layer includes, for example, a material that creates a tension stress while being heated. The material can be, for example, silicon oxide or silicon nitride. In addition, the thickness of the SAB layer is from about 500 .ANG. to about 5000 .ANG., for example. [0016] According to a method of fabricating a semiconductor device of an embodiment of the present invention, the source region and the drain region corresponding thereto in the substrate and adjacent to the sidewalls of each of the gate structures are formed by an ion implantation process. [0017] According to a method of fabricating a semiconductor device of a preferred embodiment of the present invention, the anneal process comprises a rapid thermal anneal (RTA) process, for example. [0018] According to a method of fabricating a semiconductor device of an embodiment of the present invention, the step of forming the self-aligned salicide forms a metal layer over the substrate, covering a reserved SAB layer, the gate structure which is exposed, and the exposed surface of the substrate. A thermal process is performed so that a portion of the metal layer reacts to form a salicide layer. The unreacted metal layer is then removed. [0019] The SAB layer of the present invention creates a tension stress which will change the lattice distance in the channel region of the substrate under the gate structure. Accordingly, the electron mobility in the channel region of the substrate under the gate structure is improved. The device performance is also improved. In addition, according to the present invention, a semiconductor process is conducted while the lattice distance is adjusted without additional processes and costs. [0020] The present invention provides a method of adjusting a lattice distance of a device channel. The method provides a substrate with a device formed over the substrate. The device at least comprises a gate structure and a channel region. A lattice adjusting layer is formed to cover the device. A thermal process is performed. During the thermal process, the lattice adjusting layer creates a tension stress so that a lattice distance of the channel region is changed. [0021] According to a method of adjusting a lattice distance of a device channel of a preferred embodiment of the present invention, the material of the lattice adjusting layer comprises a material that creates a tension stress while being heated. The material can be, for example, silicon oxide or silicon nitride. The thickness of the lattice adjusting layer is from about 500 .ANG. to about 5000 .ANG., for example. [0022] According to a method of adjusting a lattice distance of a device channel of an embodiment of the present invention, the anneal process can be, for example, a rapid thermal anneal (RTA) process. Continue reading about Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel... Full patent description for Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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