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  Method of fabricating metal oxide semiconductor transistorUSPTO Application #: 20070122924Title: Method of fabricating metal oxide semiconductor transistor Abstract: A masking layer is formed over a substrate. The substrate and the masking layer are patterned to form trenches that partitions the substrate into first doping type semiconductor strips. An isolation layer is formed inside the trenches such that the surface of the isolation layer is below the upper surface of the first doping type semiconductor strips. A gate oxide layer is formed on the sidewalls of the first doping type semiconductor strips. Gates are formed over the substrate. The gates cover the masking layer above the first doping type semiconductor strips and the isolation layer inside the trenches. The gates are set in a direction perpendicular to the first doping type semiconductor strips. Spacers are formed on the sidewalls of the gates and the first doping type semiconductor strips. Second doping type source/drain regions are formed in the first doping type semiconductor strips on each side of the gates. (end of abstract) Agent: Jianq Chyun Intellectual Property Office - Taipei, TW Inventors: Wen-Shiang Liao, Wei-Tsun Shiau USPTO Applicaton #: 20070122924 - Class: 438022000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Device Or Circuit Emissive Of Nonelectrical Signal The Patent Description & Claims data below is from USPTO Patent Application 20070122924. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This is a divisional application of patent application Ser. No. 11/162,080, filed on Aug. 29, 2005. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a method of fabricating an integrated circuit device. More particularly, the present invention relates to a method of fabricating a metal oxide semiconductor (MOS) transistor structure. [0004] 2. Description of the Related Art [0005] With the reduction of line width in metal oxide semiconductor (MOS) fabrication, leakage current in areas between the source and the drain away from the gate is increasingly significant. Although the leakage current can be reduced through a reduction in the thickness of the gate dielectric layer, it is no longer effective when the line width drops to 0.1 .mu.m or below. To deal with this problem, Professor Chenming Hu of the University of California at Berkley has proposed two methods. The first method is to use an extremely thin first doping type semiconductor substrate to fabricate MOSFET so that the substrate no longer has an area away from the gate and hence a leakage current no longer exists. The second method is to use a double gate structure. A gate dielectric layer in the double gate structure surrounds the channel region so that the entire channel region is subjected to the influence of the gate electric field. Ultimately, the `on` current of the device is increased and the leakage current is reduced. [0006] A fin-type field effect transistor (FinFET) that combines the two aforementioned concepts is shown in FIGS. 1A to 1C. FIG. 1A is a top view of a conventional FinFET device. FIGS. 1B and 1C are schematic cross-sectional views along the cutting lines I-I' and II-II' in FIG. 1A. The fin-type field effect transistor is formed in the following steps. First, a silicon-on-insulator (SOI) substrate 100 is provided. The silicon layer (not shown, but is a precursor of the layer labeled 120) on the insulation layer 105 has a thickness of about 100 nm. A thermal oxidation process is carried out to trim the silicon layer into one having a thickness of about 50 nm. Thereafter, a masking layer 110 fabricated from a low-temperature oxide (LTO) material is formed over the silicon layer. After that, a 100 KeV electron beam photolithographic and anisotropic etching process is carried out to define the hard masking layer 110 and the silicon layer. Hence, a fin-like silicon layer 120 having a width between 20 nm to 50 nm is formed. The narrowness of the silicon layer 120 can be seen in FIGS. 1A through 1C. Next, a polysilicon silicon-germanium (poly Si--Ge) layer (not shown, but is a precursor of the layers labeled 140 and 150) and a hard masking layer 130 fabricated from a low-temperature oxide material are sequentially formed over the substrate 100. The poly Si--Ge layer and the hard masking layer 130 are patterned to form a raised source 140 and a drain 150 having a thickness much larger than the fin-like silicon layer 120. [0007] Thereafter, a silicon nitride layer (not shown, but is a precursor to the layer labeled 160) is formed over the SOI substrate 100 and then an anisotropic etching operation is carried out to form spacers 160. In the anisotropic etching operation, an over-etching operation is carried out after the silicon nitride layer on the hard masking 130 is completely removed. Thus, the thin silicon nitride layer on the sidewalls of the fin-like silicon layer 120 is completely removed while spacers 160 are retained on the sidewalls of the raised source 140 and drain 150 as shown in FIGS. 1A and 1B. Thereafter, the sidewalls of the fin-like silicon layer 120 are oxidized to form gate oxide layers 170. Another polysilicon silicon-germanium (not shown, but is the precursor to the layer labeled 180) is formed over the SOI substrate 100 filling the gap 190 between the spacers 160. After that, the polysilicon silicon-germanium layer is patterned to form a gate 180. [0008] In the aforementioned method of fabricating the FinFET, an electron beam photolithographic process is used to define the fin-like silicon layer 120. Hence, the fin-like silicon layer 120 can be reduced to a width between 20 nm to 50 nm to prevent a leakage current. In addition, as shown in FIGS. 1A and 1C, the two sidewalls of the fin-like silicon layer 120 are designed to sense the electric field produced by the gate 180. Hence, the device can have a larger `on` current. However, the devices need to be formed on an expensive silicon-on-insulator substrate, thereby increasing the production cost. Besides, the FinFET fabrication process involves some quite complicated steps. SUMMARY OF THE INVENTION [0009] Accordingly, at least one objective of the present invention is to provide a metal oxide semiconductor (MOS) transistor structure having a lower production cost. [0010] At least a second objective of the present invention is to provide a method of fabricating a metal oxide semiconductor (MOS) transistor that can simplify the production process. [0011] To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a metal oxide semiconductor (MOS) transistor structure. The MOS transistor comprises a first doping type semiconductor substrate, a masking layer, an isolation layer, a plurality of gates, a gate oxide layer, a plurality of spacers and a plurality of second doping type source/drain regions. The first doping type semiconductor substrate has a plurality of trenches that patterns out a plurality of first doping type semiconductor strips. The masking layer is disposed on the first doping type semiconductor substrate. The isolation layer is disposed in the trenches such that the surface of the isolation layer is below the upper surface of the first doping type semiconductor strips. The gates are disposed over the first doping type semiconductor strips and oriented in a direction perpendicular to the first doping type semiconductor strips. The gate oxide layer is disposed between the sidewall of the first doping type semiconductor strips and the gates. The spacers are disposed on the sidewalls of the gates and the first doping type semiconductor strips. The second doping type source/drain regions are disposed in the first doping type semiconductor strips on each side of the gate. [0012] According to the MOS transistor structure of the present embodiment, the MOS transistor further comprises a pad oxide layer disposed between the upper surface of the first doping type semiconductor strips and the masking layer. [0013] According to the MOS transistor structure of the present embodiment, the MOS transistor further comprises a second doping type lightly doped region disposed in the first doping type semiconductor strips on each side of the gate. [0014] According to the MOS transistor structure of the present embodiment, the MOS transistor further comprises a metal silicide layer disposed over the gates and the source/drain regions. [0015] According to the MOS transistor structure of the present embodiment, the material constituting the isolation layer comprises silicon oxide. [0016] According to the MOS transistor structure of the present embodiment, the MOS transistor includes an n-type metal oxide semiconductor (n-MOS) transistor and a p-type metal oxide semiconductor (p-MOS) transistor. [0017] According to the MOS transistor structure of the present embodiment, the first doping type material is a p-doped material and the second doping type material is an n-doped material. [0018] According to the MOS transistor structure of the present embodiment, the first doping type material is an n-doped material and the second doping material type is a p-doped material. [0019] The present invention also provides a method of fabricating a metal oxide semiconductor (MOS) transistor comprising the following steps. First, a first doping type semiconductor substrate is provided. A masking layer is formed over the first doping type semiconductor substrate. Thereafter, a patterned photoresist layer is formed over the masking layer. Using the patterned photoresist layer as a mask, the first doping type semiconductor substrate and the masking layer are patterned to form a plurality of trenches that partitions the first doping type semiconductor substrate into a plurality of first doping type semiconductor strips. After that, an isolation layer is formed inside the trenches such that the surface of the isolation layer is below the upper surface of the first doping type semiconductor strips. Next, a gate oxide layer is formed on the sidewalls of the first doping type semiconductor strips. A plurality of gates is formed over the first doping type semiconductor substrate. The gates cover the masking layer above the first doping type semiconductor strips and the isolation layer inside the trenches. Furthermore, the gates are set in a direction perpendicular to the first doping type semiconductor strips. Thereafter, a plurality of spacers is formed on the sidewalls of the gates and the first doping type semiconductor strips. Finally, a plurality of second doping type source/drain regions is formed in the first doping type semiconductor strips on each side of the gates. [0020] According to the method of fabricating a MOS transistor of the present embodiment, the method further comprises forming a plurality of second doping type lightly doped regions in the first doping type semiconductor strips on each side of the gates. [0021] According to the method of fabricating a MOS transistor of the present embodiment, the method further comprises forming a metal silicide layer over the gates and the source/drain regions. Continue reading... Full patent description for Method of fabricating metal oxide semiconductor transistor Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method of fabricating metal oxide semiconductor transistor patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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