Method of fabricating array substrate having double-layered patterns -> Monitor Keywords
Fresh Patents
Monitor Patents Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents Browse Locations
site info Site News  |  monitor Monitor Keywords  |  monitor archive Monitor Archive  |  organizer Organizer  |  account info Account Info  |  
08/31/06 - USPTO Class 349 |  131 views | #20060192907 | Prev - Next | About this Page  349 rss/xml feed  monitor keywords

Method of fabricating array substrate having double-layered patterns

USPTO Application #: 20060192907
Title: Method of fabricating array substrate having double-layered patterns
Abstract: An array substrate having double-layered metal patterns for use in a liquid crystal display device and a manufacturing method thereof are disclosed in the present invention. The array substrate includes a gate electrode and a gate line each having a molybdenum alloy (Mo-alloy) layer and a copper (Cu) layer configured sequentially on a substrate; a gate insulation layer on the substrate to cover the gate electrode and the gate line; an active layer arranged on the gate insulation layer in a portion over the gate electrode; an ohmic contact layer on the active layer; a data line on the gate insulation layer, the data line crossing the gate line and defining a pixel region; source and drain electrodes on the ohmic contact layer, the source electrode extending from the data line, and the drain electrode spaced apart from the source electrode; a passivation layer on the gate insulation layer covering the data line and the source and drain electrode, the passivation layer having a drain contact hole exposing a portion of the drain electrode; and a pixel electrode configured on the passivation layer in the pixel region, the pixel electrode electrically contacting the drain electrode through the drain contact hole. (end of abstract)



Agent: Mckenna Long & Aldridge LLP - Washington, DC, US
Inventors: Oh-Nam Kwon, Kyoung-Mook Lee, Nack-Bong Choi
USPTO Applicaton #: 20060192907 - Class: 349043000 (USPTO)

Method of fabricating array substrate having double-layered patterns description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20060192907, Method of fabricating array substrate having double-layered patterns.

Brief Patent Description - Full Patent Description - Patent Application Claims
  monitor keywords



[0001] This application claims the benefit of the Korean Application No. P2002-0069285 filed on Nov. 8, 2002, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a liquid crystal display device, and more particularly, to an array substrate having double-layered metal patterns and a manufacturing method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for increasing a picture quality in the liquid crystal display device and a process stability during the fabrication process.

[0004] 2. Discussion of the Related Art

[0005] In general, since flat panel display devices are thin, light weight, and have low power consumption, they have been used for displays of portable devices. Among the various types of flat panel display devices, liquid crystal display (LCD) devices are widely used for laptop computers and desktop computer monitors because of their superiority in resolution, color image display, and display quality.

[0006] Optical anisotropy and polarization properties of liquid crystal molecules are utilized to generate a desired image. Liquid crystal molecules have a specific alignment that results from their own peculiar characteristics. The specific alignment can be modified by electric fields that are applied upon the liquid crystal molecules. In other words, the electric fields applied upon the liquid crystal molecules can change the alignment of the liquid crystal molecules. Due to optical anisotropy, incident light is refracted according to the alignment of the liquid crystal molecules.

[0007] Specifically, the LCD devices include upper and lower substrates having electrodes that are spaced apart and face each other, and a liquid crystal material is interposed therebetween. Accordingly, when a voltage is applied to the liquid crystal material through the electrodes of each substrate, an alignment direction of the liquid crystal molecules is changed in accordance with the applied voltage in order to display images. By controlling the applied voltage, the LCD device provides various transmittances for rays of light to display image data.

[0008] The liquid crystal display (LCD) devices are widely applied in office automation (OA) and video equipment due to their characteristics of light weight, thin design, and low power consumption. Among different types of LCD devices, active matrix LCDs (AM-LCDs) having thin film transistors and pixel electrodes arranged in a matrix form offer high resolution and superiority in displaying moving images. A typical LCD panel has an upper substrate, a lower substrate, and a liquid crystal material layer interposed therebetween. The upper substrate, referred to as a color filter substrate, includes a common electrode and color filters. The lower substrate, referred to as an array substrate, includes switching elements such as thin film transistors (TFT's) and pixel electrodes.

[0009] As previously described, the operation of an LCD device is based on the principle that the alignment direction of the liquid crystal molecules depends upon applied electric fields between the common electrode and the pixel electrode. Accordingly, the liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon the polarity of the applied voltage.

[0010] FIG. 1 is an expanded perspective view illustrating a related art active matrix LCD device. As shown in FIG. 1, the LCD device 11 includes an upper substrate 5, referred to as a color filter substrate, and a lower substrate 10, referred to as an array substrate, having a liquid crystal layer 9 interposed therebetween. On the upper substrate 5, a black matrix 6, and a color filter layer 7 are formed in a shape of an array matrix including a plurality of red (R), green (G), and blue (B) color filters surrounded by the black matrix 6. Additionally, a common electrode 18 is formed on the upper substrate 5 to cover the color filter layer 7 and the black matrix 6.

[0011] On the lower substrate 10, a plurality of thin film transistors T are formed in a shape of an array matrix corresponding to the color filter layer 7. A plurality of crossing gate lines 14 and data lines 22 are perpendicularly positioned such that each thin film transistor T is located adjacent to each intersection of the gate lines 14 and the data lines 22. Furthermore, a plurality of pixel electrodes 17 are formed on a pixel region P defined by the gate lines 14 and the data lines 22 of the lower substrate 10. The pixel electrode 17 includes a transparent conductive material having high transmissivity, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). Although not shown in FIG. 1, the LCD device 11 includes a backlight under the lower substrate 10. The backlight (not shown) irradiates light towards the lower and upper substrates 10 and 5.

[0012] In the related art LCD device shown in FIG. 1, a scanning signal is applied to a gate electrode of the thin film transistor T through the gate line 14, and a data signal is applied to a source electrode of the thin film transistor T through the data line 22. As a result, the liquid crystal molecules of the liquid crystal layer 9 are re-aligned and re-arranged by operation of the thin film transistor T, and incident light from the backlight (not shown) passing through the liquid crystal layer 9 is controlled to display an image. Namely, the electric fields induced between the pixel and common electrodes 17 and 18 re-arrange the liquid crystal molecules of the liquid crystal layer 9 so that the incident light can be converted into the desired images in accordance with the induced electric fields.

[0013] There are various factors that affect and define a picture quality of the LCD device 11. Among those various factors, electrical resistance of the gate and data lines 14 and 22 is an important requisition for achieving the improved picture quality in the LCD device 11. As the gate and data lines 14 and 22 have lower electrical resistance, the signal delay is reduced in those lines and thus the picture quality can become improved.

[0014] For the purpose of obtaining the reduced signal delay, copper (Cu) having relatively low electrical resistance is used for the gate and data lines 14 and 22. However, since copper (Cu) does not adhere well to the substrate, a buffer metal layer, for example, titanium (Ti) or molybdenum (Mo), may be used beneath the copper (Cu).

[0015] FIG. 2 is a cross-sectional view taken along line II-II' of FIG. 1, illustrating a pixel of a related art array substrate.

[0016] As shown in FIG. 2, the thin film transistor T is formed on an upper surface of the lower substrate 10. The thin film transistor T includes a gate electrode 30, an active layer 34, an ohmic contact layer 36, a source electrode 38, and a drain electrode 40. Between the gate electrode 30 and the active layer 34, a gate insulation layer 32 is interposed to protect the gate electrode 30 and the gate line 14. As shown in FIG. 2, the gate electrode 30 extends from the gate line 14 and the source electrode 38 extends from the data line 22. The gate line 14 and the gate electrode 30 are formed of the same material, and the data line 22 and the source and the drain electrodes 38 and 40 are formed of the same material. The active layer 34 and the ohmic contact layer 36 are formed of silicon, but the active layer 34 is intrinsic silicon and the ohmic contact layer 36 are n.sup.+-doped silicon. A passivation layer 42 is formed on the thin film transistor T for protection. In the pixel region P defined by the pair of the gate and data lines 14 and 22, the pixel electrode 17 that is formed of a transparent conductive material is disposed on the passivation layer 42 while contacting the drain electrode 40 through a contact hole.

[0017] In the related art array substrate of FIG. 2, the gate line 14 and the gate electrode 30 have a double-layered structure having copper/titanium (Cu/Ti) double layers or copper/molybdenum (Cu/Mo) layers. Also the data line 22, the source electrode 38 and the drain electrode 40 have a double-layered structure having copper/titanium (Cu/Ti) double layers or copper/molybdenum (Cu/Mo) layers. For example, a lower part 14a of the gate line 14 is the titanium (Ti) or molybdenum (Mo) layer, and an upper part 14b of the gate line 14 is the copper (Cu) layer.

[0018] If the above-mentioned metal structures only have a single layer of copper (Cu), OXONE (2KHSO.sub.5.KHSO.sub.4.K.sub.2SO.sub.4) is generally used as an etchant to form the copper gate line and electrode. When forming the double-layered metal structure of copper/titanium (Cu/Ti), a mixed solution of OXONE, hydrogen fluoride (HF) and ammonium fluoride (NH.sub.4F) is frequently used. However, when etching the copper/titanium (Cu/Ti) double layers using the mixed solution of OXONE, hydrogen fluoride (HF) and ammonium fluoride (NH.sub.4F) to form the gate line and electrode, the mixture damages and unevenly etches the surface of the substrate due to that fact that F.sup.- ions are contained in the mixture solution. As a result, the damages and uneven etch of the substrate surface cause a decreased degree of image quality in the liquid crystal display device, such as generation of stained and spotted images.

[0019] Furthermore, when the copper/titanium (Cu/Ti) double layers are applied for the data line, the source electrode and the drain electrode, the underlying gate insulation layer is definitely etched and damaged by the etchant. Therefore, the damages and uneven etch of the gate insulation layer also cause the decreased degree of image quality in the liquid crystal display device.

[0020] FIG. 3 is a photograph of partially-etched copper/titanium (Cu/Ti) double layers taken by a SEM (Scanning Electron Microscope); and FIG. 4 is an enlarged view showing a portion of the etched copper/titanium (Cu/Ti) double layers of FIG. 3.

[0021] In FIGS. 3 and 4, a titanium (Ti) layer 52a is first formed on a substrate 50 and a copper (Cu) layer 52b is then formed on the titanium (Ti) layer. Then the copper/titanium (Cu/Ti) double layers 52 are wet-etched by the above-mentioned mixed solution. As indicated in FIG. 3, the substrate 50 has an irregularly etched and damaged surface 54.

[0022] In FIG. 4, it is much more noticeable that the surface of substrate 50 is severely corroded, although the Ti layer 52a and the Cu layer 52b are normally etched. Particularly, since the substrate 50 is glass, it is etched as much as about 400 angstroms (.ANG.) from its primary surface, as indicated in FIG. 4.

[0023] When using the copper/molybdenum (Cu/Mo) layers for the double-layered metal patterns, the underlying molybdenum (Mo) layer is damaged and the copper (Cu) layer is undercut by the damaged molybdenum (Mo) layer, although the glass substrate is not damaged. Namely, the etchant for the copper/molybdenum (Cu/Mo) layers does not affect the glass substrate, but it damages the Mo layer and makes the Cu layer come off the substrate.

Continue reading about Method of fabricating array substrate having double-layered patterns...
Full patent description for Method of fabricating array substrate having double-layered patterns

Brief Patent Description - Full Patent Description - Patent Application Claims

Click on the above for other options relating to this Method of fabricating array substrate having double-layered patterns patent application.
###
monitor keywords

How KEYWORD MONITOR works... a FREE service from FreshPatents
1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored.
3. Each week you receive an email with patent applications related to your keywords.  
Start now! - Receive info on patent apps like Method of fabricating array substrate having double-layered patterns or other areas of interest.
###


Previous Patent Application:
System and method for defect localization on electrical test structures
Next Patent Application:
Thin film transistor array panel and manufacturing method thereof
Industry Class:
Liquid crystal cells, elements and systems

###

FreshPatents.com Support
Thank you for viewing the Method of fabricating array substrate having double-layered patterns patent info.
IP-related news and info


Results in 0.25471 seconds


Other interesting Feshpatents.com categories:
Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , 174
filepatents (1K)

* Protect your Inventions
* US Patent Office filing
patentexpress PATENT INFO