| Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the same -> Monitor Keywords |
|
|
  Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the sameUSPTO Application #: 20060108650Title: Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the same Abstract: A highly integrated semiconductor device operates at a high speed due to low resistance at the gate electrode and minimal parasitic capacitance between the gate electrode and substrate. A gate pattern is formed on a substrate, and an insulating layer is formed over the substrate including over the gate pattern. The thickness of the insulating layer is reduced until the upper surface thereof beneath the level of the upper surface of the gate electrode. A conductive layer is then formed on the substrate, and is anisotropically etched to thereby form wings constituting a first spacer on upper sidewalls of the gate pattern. Then, the insulating layer is etched to leave a portion thereof beneath the wings. This remaining portion of the insulating layer constitutes a capacitance preventative layer that serves as a measure against the subsequent forming of a parasitic capacitor when source/drain electrodes are formed by implanting ions into the substrate and heat-treating the same. (end of abstract) Agent: Volentine Francos, & Whitt PLLC - Reston, VA, US Inventors: Chan-Hyung Cho, Sung-Gyu Park USPTO Applicaton #: 20060108650 - Class: 257401000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Field Effect Transistor In Integrated Circuit, With Specified Physical Layout (e.g., Ring Gate, Source/drain Regions Shared Between Plural Fets, Plural Sections Connected In Parallel To Form Power Mosfet) The Patent Description & Claims data below is from USPTO Patent Application 20060108650. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCES TO RELATED PARENT APPLICATION [0001] This application is a divisional of U.S. patent application Ser. No. 10/780,851 filed on 19 Feb. 2004, and claims priority under 35 U.S.C. .sctn.119 from Korean Patent Application 2003-012788, filed 28 Feb. 2003, the contents of which are hereby incorporated by reference in their entirety as if fully set forth herein. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device having a mushroom- or T-shaped gate electrode, and to a method of fabricating the mushroom or T-shaped gate electrode. More specifically, the present invention relates to a semiconductor device having a gate electrode whose upper surface is relatively large so as to accommodate a metal silicide, and to a method of fabricating a gate electrode wherein the upper surface of the gate electrode is enlarged. [0004] 2. Description of the Related Art [0005] Recent sub-micron integrated circuit technology aims at continuously reducing the line width and contact area of the semiconductor device, whereby the length of the gate lines of integrated circuits is continuously decreasing. In general, shortening the gate line increases the electrical resistance of the gate line (hereinafter, referred to as line resistance), resulting in a corresponding reduction in the operating speed of the gate line. That is, the operating speed in an integrated circuit is mainly dependent on a delay time, and the line resistance and parasitic capacitance between the gate lines have a decisive effect on the delay time. Accordingly, increases in the operating speed of the integrated circuit must be achieved by reducing the line resistance or reducing the parasitic capacitance by widening the space between the gate lines. [0006] Most of the technology has focused on decreasing the line resistance to improve the operating speed of the integrated circuit because the alternative solution of widening the space between the gate lines runs counter to the aim of achieving a high degree of integration of the integrated circuit. A recent technological trend involves the use of a polycide layer to minimize the line resistance. Specifically, a silicide layer including a metal having a high melting point is coated on an upper portion of a gate electrode formed of polysilicon, and the silicide layer is incorporated with the gate electrode by a heat treatment to form the polycide layer. [0007] However, when the line width of the integrated circuit is less than 0.13 .mu.m, the length and width of the gate electrode are correspondingly small, and the surface area of the gate electrode is also extremely small. Accordingly, the contact area between the gate electrode and the metal used to form the silicide layer is so small that the silicide layer is not sufficiently incorporated into the gate electrode by the heat treatment. That is, when the line width is less than 0.13 .mu.m, the resistance of the polycide layer on the gate electrode is unstable and hence, the polycide layer does not reduce the electrical resistance at the gate electrode. [0008] Delay time also results from the parasitic capacitance generated in a region of overlap between the gate electrode and the substrate. In the fabricating of semiconductor devices, the gate electrode is first formed of polysilicon on the substrate such that a dimension of the gate electrode conforms to the length of a channel layer under the gate electrode, and then source/drain electrodes are subsequently formed through an ion implantation process. A plurality of dopants are injected into an active region of the substrate to form the source/drain electrodes, and a heat treatment is performed for stabilizing the substrate. However, the dopants diffuse to the edge portion of the gate electrode due to the heat. Accordingly, the source and drain electrodes extend to locations beneath the gate electrode at both edge portions thereof. Accurdingly, the channel layer is shortened by an amount corresponding to the amount of overlap between the gate electrode and the source/drain electrodes (short channel effect). The overlapping portion acts as a parasitic capacitor between the gate electrode and the substrate because the overlapping portion is electrically non-conductive. When an electrical current is applied to the source electrode, the parasitic capacitor is first charged and then, the current passes into the drain electrode through the channel layer. Therefore, a time delay is produced according to the time it takes to charge the parasitic capacitor. That is, the parasitic capacitance (hereinafter referred to as "overlay parasitic capacitance") reduces the operating speed of the integrated circuit. The operating speed is also reduced due to an overlay parasitic capacitor created as the result of a halo ion implantation process for preventing the diffusion of the source/drain dopants. [0009] Ways to improve the resistance characteristic of the polycide gate electrode have been researched in connection with the fabricating of semiconductor devices having a design rule of less than 0.1 .mu.m. For example, U.S. Pat. No. 6,169,017 (issued to Tong-Hsin Lee) discloses a technique of enlarging the upper surface of the gate electrode with which the silicide layer is to contact, whereupon the gate electrode is T-shaped or mushroom-shaped. Furthermore, Japanese Laid-Open Patent Publication No. 2000-36594 discloses a method of fabricating a polycide gate electrode, wherein polysilicon is twice deposited on a substrate such that an upper portion of the gate electrode is larger than the lower portion thereof. However, these techniques each fail to prevent the occurrence of a time delay due to the overlay parasitic capacitance between the gate electrode and substrate. SUMMARY OF THE INVENTION [0010] Accordingly, an object of the present invention is to provide a method of forming a gate electrode having a stable polycide layer and yet wherein overlay parasitic capacitance between the gate electrode and the substrate is minimal. [0011] Another object of the present invention is to provide a highly integrated semiconductor device having a high operating speed, and to provide a method of fabricating the same. [0012] Likewise, a more specific object of the present invention is to provide a semiconductor device whose gate electrode offers little resistance and yet gives rise to hardly any parasitic capacitance. [0013] According to one aspect of the present invention, a method of forming a gate structure in a semiconductor device comprises a) forming a first insulating layer on a semiconductor substrate, forming a layer of conductive material on the first insulating layer, and patterning the first conductive layer to form at least one gate pattern, b) forming a second insulating layer on the gate pattern and substrate, c) reducing the thickness of the second insulating layer until the upper surface thereof becomes situated beneath the level of the upper surface of the gate pattern, d) forming a second conductive layer over the resultant structure, e) selectively removing portions of the second conductive layer such that a spacer of the conductive material is formed at both sides of an upper portion of the gate pattern, and f) subsequently removing portions of the second insulating layer other than those located beneath the spacer. [0014] The thickness of the second insulating layer is preferably reduced by a chemical mechanical polishing (CMP) process followed by a wet-etch process. After the second conductive layer is formed on the second insulating layer and the gate pattern, the second conductive layer is selectively etched by an anisotropic etching process. As a result, the spacer formed by the conductive material at both sides of the upper portion of the gate pattern enlarges the surface area of the gate pattern. [0015] According to another aspect of the present invention, a method of forming a semiconductor device comprises a) forming a first insulating layer on a semiconductor substrate, forming a layer of conductive material on the first insulating layer, and patterning the first conductive layer to form at least one gate pattern, b) forming a second insulating layer on the gate pattern and substrate, c) reducing the thickness of the second insulating layer until the upper surface thereof becomes situated beneath the level of the upper surface of the gate pattern, d) forming a second conductive layer over the resultant structure, e) selectively removing portions of the second conductive layer such that a first spacer of the conductive material is formed at both sides of an upper portion of the gate pattern, f) subsequently removing portions of the second insulating layer other than those located beneath the spacer, g) implanting ions at a relatively low concentration into the substrate at the sides of the gate pattern to form a lightly-doped source/drain region, h) forming a fourth insulating layer over the resultant structure, i) selectively removing portions of the fourth insulating layer to form a second spacer at the sides of the gate pattern, j) subsequently implanting ions at a relatively heavy concentration into the substrate at the sides of the gate pattern to form a heavily-doped source/drain region, k) subsequently heat-treating the substrate to chemically bond the dopants to the substrate, and m) forming a third conductive layer on the gate pattern and first spacer. [0016] In addition, portions of the first insulating layer may be etched away with those of the second insulating layer (f) such that the surface of the substrate is exposed. In this case, a third insulating layer is formed over the entire surface of the substrate and on the enlarged gate pattern. Subsequently, the lightly concentrated ions are implanted into the substrate (g) using the gate pattern as a mask. [0017] Preferably, the fourth insulating layer is formed (h) on the third insulating layer using a CVD or a PVD process, and is subsequently selectively etched (i) using an anisotropic etching process. The heavily concentrated of ions are implanted into the substrate using the enlarged gate pattern and the second spacer as masks. [0018] According to still another aspect of the present invention, a semiconductor device comprises a) a semiconductor substrate, b) a gate insulating layer disposed on the substrate, c) a T- or mushroom-shaped gate electrode including a man body disposed on the gate insulating layer and wings extending laterally from an upper portion of the main body, e) a capacitance preventative layer of insulating material disposed under the wings of the T- or mushroom-shaped gate electrode, d) a discrete spacer disposed at both sides of the gate electrode laterally of the capacitance preventative layer and, e) a source electrode and a drain electrode defined at opposite sides of the gate electrode. [0019] The semiconductor substrate includes an active region defined by an isolation structure such as a shallow trench isolation structure. The gate-insulating layer is coated on the substrate in the active region. The capacitance preventative layer contacts the main body of the gate electrode and gate insulating layer. [0020] Preferably, the main body and wings of the gate electrode comprise polysilicon, and the capacitance preventative layer is a low-temperature oxide (LTO). In addition, the semiconductor device of the present invention may further comprise an anti-diffusion layer for preventing ion dopants in the source/drain region of the substrate from diffusing into a channel region located beneath the gate electrode. The gate electrode preferably also comprises a metal silicide layer on the main body and wings thereof to thereby reduce the electrical resistance of the gate electrode. The metal silicide layer may also be disposed on the source/drain electrode to thereby to reduce the electrical resistance thereof. BRIEF DESCRIPTION OF THE DRAWINGS Continue reading... Full patent description for Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the same or other areas of interest. ### Previous Patent Application: Self-aligned trench filling for narrow gap isolation regions Next Patent Application: Lowered source/drain transistors Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the same patent info. IP-related news and info Results in 2.62494 seconds Other interesting Feshpatents.com categories: Software: Finance , AI , Databases , Development , Document , Navigation , Error |
||
