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Method of eliminating photoresist poisoning in damascene applicationsRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects), Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization), With Formation Of Opening (i.e., Viahole) In Insulative LayerMethod of eliminating photoresist poisoning in damascene applications description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060205206, Method of eliminating photoresist poisoning in damascene applications. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCES TO RELATED APPLICATIONS [0001] This application is a continuation of co-pending U.S. patent application Ser. No. 10/718,887, filed Nov. 21, 2003, which is a continuation of U.S. patent application Ser. No. 09/977,008, filed Oct. 11, 2001, now U.S. Pat. No. 6,656,837, issued Dec. 12, 2003. Each of the aforementioned related patent applications is herein incorporated by reference. BACKGROUND OF THE DISCLOSURE [0002] 1. Field of the Invention [0003] The invention relates to the fabrication of integrated circuits and to a process for depositing dielectric layers on a substrate and the structures formed by the dielectric layer. [0004] 2. Description of the Related Art [0005] One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric layers on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired layer. [0006] Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 .mu.m and even 0.18 .mu.m feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries. [0007] To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (dielectric constant<4.0) to also reduce the capacitive coupling between adjacent metal lines. One such low k material is spin-on glass, such as un-doped silicon glass (USG) or fluorine-doped silicon glass (FSG), which can be deposited as a gap fill layer in a semiconductor manufacturing process and silicon oxycarbide which can used as a dielectric layer in fabricating damascene features. [0008] One conductive material gaining acceptance is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 .mu..OMEGA.-cm compared to 3.1 .mu..OMEGA.-cm for aluminum), a higher current and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state. [0009] One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed. [0010] One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, i.e. vias, and horizontal interconnects, i.e., lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed. [0011] However, when silicon oxycarbide layers or silicon carbide layers are used as the low k material in damascene formation, it has been difficult to produced aligned features with little or no defects. It as been observed that photoresist materials deposited on the silicon oxycarbide layers or the silicon carbide layers may be contaminated with nitrogen deposited with those layers or nitrogen that diffuses through those layers. For example, reaction of organosilicon compounds with nitrous oxide can contaminate the silicon oxycarbide layer with nitrogen. Photoresist materials contaminated with nitrogen becomes less sensitive to radiation. Any photoresist material that is not sensitive to radiation is not removed by subsequent photoresist stripping processes and remains as residue. This residue can result in detrimentally affecting subsequent etching processes and result in misaligned and malformed features. [0012] Therefore, there remains a need for an improved process for depositing photoresist material on silicon oxycarbide or silicon carbide dielectric layers. SUMMARY OF THE INVENTION [0013] Aspects of the invention generally provide a method for depositing a silicon oxycarbide layer or silicon carbide layer having a low dielectric constant with reduced photoresist poisoning. In one aspect, the invention provides a method for processing a substrate including depositing a dielectric layer containing silicon and carbon, treating a surface of the dielectric layer comprising silicon and carbon by exposing the dielectric layer to a plasma of an inert gas, and depositing a photoresist on the dielectric layer. [0014] The method may further include patterning and etching the photoresist layer to expose the dielectric layer comprising silicon and carbon, and then etching the dielectric layer to form at least a portion of a damascene definition prior to depositing one or more conductive materials in the damascene definition to form a damascene structure. The dielectric layer may have a carbon content between about 5 and about 30 atomic percent excluding hydrogen atoms. The silicon and carbon containing layer can be an amorphous silicon carbide layer that may be doped with oxygen, nitrogen, or both or a silicon oxycarbide layer doped with nitrogen. [0015] In another aspect of the invention, a method is provided for processing a substrate including depositing a first dielectric layer comprising silicon, carbon, and nitrogen, depositing a nitrogen-free silicon and carbon containing material in situ on the dielectric layer, depositing a second dielectric layer comprising silicon, oxygen, and carbon on the nitrogen-free silicon and carbon containing material by chemical vapor deposition, and depositing a photoresist on the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS [0016] So that the manner in which the above aspects of the invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. [0017] It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. [0018] FIG. 1 is a cross-sectional diagram of an exemplary CVD reactor configured for use according to embodiments described herein; [0019] FIG. 2 is a flow chart of a process control computer program product used in conjunction with the exemplary CVD reactor of FIG. 1; [0020] FIG. 3 is a cross sectional view showing a dual damascene structure comprising the silicon carbide and silicon oxycarbide layers described herein; Continue reading about Method of eliminating photoresist poisoning in damascene applications... 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