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  Method of design analysis of existing integrated circuitsUSPTO Application #: 20060045325Title: Method of design analysis of existing integrated circuits Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout. (end of abstract)
Agent: Sterne, Kessler, Goldstein & Fox PLLC - Washington, DC, US Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg USPTO Applicaton #: 20060045325 - Class: 382145000 (USPTO) Related Patent Categories: Image Analysis, Applications, Manufacturing Or Product Inspection, Inspection Of Semiconductor Device Or Printed Circuit Board The Patent Description & Claims data below is from USPTO Patent Application 20060045325. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to a method of design analysis of existing integrated circuits, and more particularly to the determination of the location of standard cells in an image of an IC layout. [0003] 2. Background Art [0004] In the intensely competitive field of microelectronics, detailed analysis of a semiconductor integrated circuit product can provide valuable information as to how a particular technical problem was dealt with, overall strengths and weaknesses of a design approach, and the like. This information can be used to make decisions regarding market positioning, future designs and new product development. The information resulting from analysis of the product is typically provided through circuit extraction (reverse engineering), functional analysis and other technical means. At the core of this activity is the process of design analysis, which, in this context, refers to the techniques, and methodology of deriving complete or partial schematics, starting with essentially any type of integrated circuit in any process technology. For such technical information to be of strategic value it must be accurate and cost-effective, and it is very important that the information should be timely. [0005] A design analysis process typically involved skilled engineers manually extracting circuit information from a set of large "photomosaics" of an integrated circuit (IC). Photomosaics are high magnification photographs of portions of an IC mosaicked or stitched together. To properly extract the circuitry, photomosaics of each polysilicon (poly) and metal layer are required. Due to advances in image processing and electron microscopy, photomosaics have been replaced with computer workstations. Topographical images of the die can be viewed on a computer through dedicated software. Each metal layer is shown as a different colour to differentiate between each other. The layers can be selected and de-selected so the engineer can view selected layers instead of all of them. Although this technique is less time-consuming than the use of photomosaics, the engineer must still manually extract all the circuitry. What is especially time-consuming is the extraction of standard cells. Standard cells can make up a large part of an IC, yet the engineer must manually extract each standard cell individually. [0006] In order to create an efficient automated system for extracting standard cells, there are several issues that need to be addressed: [0007] A. The poly layer of each standard cell instance is usually identical, but some of the lower metal layers can be changed from one instance to another. [0008] B. The gray-scale image of every poly and metal layer is at least several gigabytes in size. [0009] C. The layers are not usually perfectly aligned with one another. It is possible that the layers can be misaligned by a few pixels. [0010] D. The poly layers typically have low contrast, high noise and contain visible distortions and brightness/contrast variations. [0011] E. The layers typically contain many thin lines (about 3-4 pixels), so the automated standard cell extraction system must be sensitive enough to account for these lines. [0012] F. The images can contain other cells that are very similar. The difference may be only in a couple of low contrast lines. [0013] In order to overcome the above-described manual process, automated systems have been designed. Such systems are described in U.S. Pat. No. 5,086,477, which issued to Yu et al on Feb. 4, 1992 and U.S. Pat. No. 5,191,213, which issued the Ahmed et on Mar. 2, 1993. [0014] In the system described in U.S. Pat. No. 5,086,477--Yu et al, the integrated circuit chip is scanned by a microscope or scanning electron microscope (SEM). The system identifies every unique cell and/or gate used in the integrated circuit. A unique abstract representation is created for each of these unique cells or gates, which are stored in a library. [0015] In this patented system, once all unique cells have been captured in a reference library, the system attempts to associate and match all abstract features contained in the layout database to the cells in the reference library using classical template matching. However because of the magnitude of data contained in a layout database for a typical modern integrated circuit, even after the data has been compressed, the processing time required to reliably extract a netlist is excessive, and Yu et al therefore teaches that the tasks should be (manually) operator directed. The difficulty and time required for the operator directed process increases with a larger number of cells or gates, since the number of template matching operations augments exponentially with the number of reference cells and/or gates. [0016] Once all reference cells in the Yu et al system have been template matched to the database, theoretically all features in the layout database will have been grouped and classified and a netlist can be constructed. If there are features of the layout data base that have not been classified, either the system must construct a new cell or gate to be added to the reference library and an operator is informed, or the operator is informed by the system and the operator performs this task. The cell to cell interconnects information extraction, which is required to construct a netlist, is said to be performed using template matching, which is very inefficient. [0017] Due to the template matching approach that is required, the Yu et al system must be limited to gate-array or very structured standard cell integrated circuit analysis in which the large majority of the cells are identical, and therefore as the size of the integrated circuits increase, its efficiency decreases. It is therefore inefficient for analysis of modern ASICs or custom integrated circuits, large and/or complex integrated circuits. The Yu et al system would also be limited to applications where many devices from a few ASIC manufacturers are investigated, due to the investment and time required to develop separate reference libraries, e.g. related to a different set of design rules. [0018] U.S. Pat. No. 5,191,213--Ahmed et al relates to a technique for removing layers of an integrated circuit and for scanning each of the layers, and does not appear to be an automated system. [0019] The paper: L. R. Avery, J. S. Crabbe, S. Al Sofi, H. Ahmed, J. R. A. Cleaver and D. J. Weaver "Reverse engineering complex application-specific integrated circuits (ASICs)" DMSMS Conference 2002, discloses an automated macro (standard cell) extraction method where via and contact information are used to find probable locations of macros. In some cases, contact information is not readily available due to imaging and/or sample preparation issues. In other cases, such as gate arrays, contact patterns are very repetitive and cannot be used for finding even a preliminary location. [0020] An example of an object localization method that uses point of interest matching and descriptors to characterize the vicinity of the point of interest is disclosed in U.S. Pat. No. 6,711,293, which issued to Lowe on Mar. 23, 2004. This method uses some statistics of histograms in vicinities of points of interest. The points of interest used in this method are pixel amplitude extremes. [0021] All of the above references are herein incorporated by reference. [0022] Therefore there is a need for a computationally affordable template matching method for finding standard cells in reverse engineered multi-layer images of an IC layout. SUMMARY OF THE INVENTION [0023] The present invention is directed to a method and apparatus for determining high probability locations of standard cells in an image of an IC layout in a computationally efficient manner. The first step is to extract and characterize the features of the IC layout. The next step is to further extract a standard cell from the layout that will be used as a template or basis for comparison. To obtain a coarse localization of possible locations, the features of the template are compared with the features of the remainder of the IC layout. The last step is to apply a fine filter on the shortlist of possible match locations to finally obtain high probability locations. An intermediate step may include putting the coarse localization through a coarse filter so that a further set of coarse filtered possible locations is achieved. [0024] In accordance with another aspect of the present invention possible locations of standard cells in an image of an IC layout are determined by first extracting points of interest from the image. To characterize each of these points of interest, bitmap descriptors are created in the vicinity of each point of interest. After these initialization steps, it is necessary to extract a first instance of a standard cell from the IC layout. The bitmap descriptors from the template are compared with the remaining bitmap descriptors of the IC layout. This comparison yields a set of similar points of interest. Votes are cast on these similar points of interest to determine the confidence level on the similarity of the so-called similar points of interest. In computing the weights of the votes, the locations on the image having a high vote count, correspond to the possible locations of standard cells. [0025] In accordance with a specific aspect of this invention, the image includes a first conductive layer of the IC and the points of interest are selected from centers of contacts on the first conductive layer, centers of vias on the first conductive layer and corners of polygons representing the first conductive layer. The bitmap descriptor comprises a grid having a number of non-overlapped rectangles, said non-overlapped rectangles represented by a first bit if they contain at least a predetermined percentage of the first conductive layer and represented by a second bit if they contain less than the predetermined percentage. Further the bitmap descriptor may be a 32-bit descriptor and the bitmap descriptors from the first instance of a standard cell comprise eight possible orientations of the standard cell. [0026] In accordance with a further aspect of the present invention a possible location of a standard cell in an image of an IC layout is determined to be a high probability match of the standard cell using a rigid comparison method. The first step is to compute the pixel gradients of the template and each possible location. Next, the dot products between the gradients of the template and each possible location are computed. Applying morphological dilation filters the dot products to remove any effect from noise or texture variations. Order statistics are computed on the filtered dot products and if the resulting statistics are less than a predefined threshold, then the possible location is a true instance of a standard cell. [0027] Other aspects and advantages of the invention, as well as the structure and operation of various embodiments of the invention, will become apparent to those ordinarily skilled in the art upon review of the following description of the invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Continue reading... Full patent description for Method of design analysis of existing integrated circuits Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method of design analysis of existing integrated circuits patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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