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Method for tracing paths within a circuitRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Routing (e.g., Routing Map, Netlisting)Method for tracing paths within a circuit description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060200787, Method for tracing paths within a circuit. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to circuit analysis, and more particularly to tracing paths within a circuit. BACKGROUND OF THE INVENTION [0002] During the design of circuits, many different devices are connected together in multiple ways. Internal paths critical to the operation of circuits such as memory should be analyzed for design and timing margins. Without such analysis, robust designs are more difficult to achieve. [0003] In particular, the issue arises for analysis and verification of third party circuits where the detailed design information such as schematics are not available. Current methods for analysis of circuits may rely on transistor level simulation of the circuit, however this may be complicated and time consuming. [0004] Accordingly, what is needed is more efficient and less time-consuming method for tracing paths within a circuit. The present invention addresses such a need. BRIEF SUMMARY OF THE INVENTION [0005] Aspects of the present invention include a method for tracing paths within a circuit. First, a transistor level netlist is received. After receiving the transistor level netlist, the transistor level netlist description is converted to a transistor level data structure. Then, the transistor level data structure is converted to a set of channel connect groups (CCG). A directed graph of the CCG may then be generated. [0006] According to the method disclosed herein, the present invention uses CCGs to represent transistor groups and provides a graph-based analysis of traversal functions, which improves the speed of path tracing and finding critical paths in a circuit. The present invention eliminates the need for simulation in order to analyze complex transistor circuits. BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS [0007] FIG. 1 is a flow diagram illustrating one embodiment of the invention for tracing paths within a circuit. [0008] FIG. 2 is a diagram illustrating one example of a transistor level representation. [0009] FIG. 3 is a diagram illustrating one example of a directed graph of channel connect groups. DETAILED DESCRIPTION OF THE INVENTION [0010] The present invention relates to circuit analysis, and more particularly to tracing paths within a circuit. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein. [0011] FIG. 1 is a flow diagram illustrating one embodiment of the invention for tracing paths within a circuit. The method of FIG. 1 may be applied to any circuit, for example a memory, other integrated circuit (IC), or a third-party circuit. In block 100, a user receives a transistor level netlist of a circuit (not shown). Transistor level netlists are well-known in the art. [0012] Optionally, the user may also receive a bitcell netlist for the circuit, which is also well known in the art, in block 110. The bitcell netlist (not shown) provides information about the bit cells within the circuit. With the bitcell netlist, a bitcell pattern may be determined in block 120 by, for example, finding all the bit nodes in the circuit. In block 130 node patterns may be matched with bit patterns by, for example, finding corresponding bit line and word line connections for each bit cell node group in the circuit block. Bitcell, wordline, and bitline data from the corecell netlist may be used hierarchically or propagated to the next level if the design representation is flattened by mapping appropriate node names. This data may be organized in different ways if used optionally with the invention. [0013] Continuing with the invention, in block 140 the transistor level netlist is converted to a transistor level data structure (not shown). A transistor level data structure is typically used by a computer program in order to process the information in the transistor level netlist. The transistor level data can be represented as link-list or associative array data structures. [0014] FIG. 2 is a schematic diagram illustrating one example of a transistor level representation 200. The transistor level representation 200 is one graphical representation of a transistor level netlist. Transistors 205-1, 205-2, 205-3, 205-4, 205-5, 205-6, 205-7, 205-8, 205-9, 205-10, 205-11, 205-12, 205-13, 205-14, 205-15, and 205-16 (collectively referred to as transistors 205) in the transistor level representation 200 are connected to one another, to power 210, and to ground 220. Each transistor 205 functionally has a gate, a source and a drain. [0015] The transistor level representation 200 is illustrated in order to simplify the explanation of conversion to channel connect groups. In block 150 of FIG. 1, the transistor level data structure is converted to a set of channel connect groups (CCGs) 230-1, 230-2, 230-3, 230-4 (collectively referred to as CCGs 230) in one embodiment of the invention. Each CCG 230 includes transistors 205 having a source or a drain connected to the source or drain of another transistor 205 in that CCG 230, and all of the transistors 205 in the CCG have a gate that is connected external to the CCG. In other words, no transistor 205 within a given CCG 230 is connected to another transistor 205 in that CCG 230 through its gate. [0016] For example, CCG 230-1 includes transistors 205-1, 205-2, 205-3, 205-4, 205-5 and 205-6. Transistor 205-1 has a gate connected to input 206-1 and a drain connected to power 210, and a source connected to transistors 205-2 and 205-5. One skilled in the art will recognize that different types of transistors may be used (for example, p or n-channel) and that in this example all the transistors may be n-channel, whereas p-channel transistors have reversed source and drain nodes, among other differences. Because transistors 205-1, 205-2 and 205-5 have drain/source connections (and they are not connected together through any of their gates) they are included in the same CCG 230-1. The gate of a transistor is considered an input to the CCG unless it is connected to a power source or to ground. [0017] Moving on from transistor 205-2, transistors 205-7 and 205-8 are connected to the gate of transistor 205-2, so transistor 205-2 is in a separate CCG 230 from transistors 205-7 and 205-8. However, transistor 2054 is connected to the drain of transistor 205-2 and to ground 220, so transistors 205-4 and 205-2 are both in CCG 230-1. Input 206-4 is connected to the gate of transistor 205-4 and therefore considered an input to CCG 230-1 [0018] Continuing from transistor 205-5, the source of transistor 205-6 is connected to the drain of transistor 205-5, therefore transistor 205-6 is also in CCG 230-1. Transistor 205-5 has input 206-5 at its gate while transistor 205-6 also has input 206-6 at its gate. Therefore, inputs 206-5 and 206-6 are both considered inputs to CCG 230-1. Transistor 205-3 has its source connected to the drain of transistor 205-6, putting transistor 205-3 in CCG 230-1 as well. Input 206-3 to the gate of transistor 205-3 is considered an input to CCG 230-1. Transistors 205-7, 205-8 and 205-12 are connected through their gates to transistor 205-3, therefore transistors 205-7, 205-8 and 205-12 are excluded from CCG 230-1. [0019] Moving on to CCG 230-2, transistor 205-7 is connected through its source to power 210, and through its drain to transistor 205-8, placing both transistors in the same group. Transistors 205-7 and 205-8 have a drain/source connection to the gates of transistors 205-10, 205-11 and 205-2, therefore transistors 205-10, 205-11 and 205-2 are in separate groups from transistors 205-7 and 205-8. Finally, transistors 205-7 and 205-8 are connected trough their gates to transistors 205-3 and 205-12, placing transistors 205-7 and 208 in a separate group. CCG 230-2 therefore includes transistors 205-7 and 205-8. Continue reading about Method for tracing paths within a circuit... Full patent description for Method for tracing paths within a circuit Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method for tracing paths within a circuit patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method for tracing paths within a circuit or other areas of interest. ### Previous Patent Application: Static timing analysis and dynamic simulation for custom and asic designs Next Patent Application: Method for describing and deploying design platform sets Industry Class: Data processing: design and analysis of circuit or semiconductor mask ### FreshPatents.com Support Thank you for viewing the Method for tracing paths within a circuit patent info. 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