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Method for testing semiconductor devices and an apparatus thereforMethod for testing semiconductor devices and an apparatus therefor description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070040570, Method for testing semiconductor devices and an apparatus therefor. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. application Ser. No. 10/954,920, filed on Sep. 30, 2004, the disclosure of which is incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] The present invention relates generally to an apparatus and method for testing semiconductor devices. More particularly, the present invention relates to a test apparatus for packaged semiconductor devices that utilizes a pick-and-place mechanism to transfer the devices between and among various locations in the apparatus. [0003] Integrated circuit (IC) devices are subjected to a variety of tests after fabrication. These tests occur before the IC is packaged and after the IC is packaged. The tests are designed to determine if the IC will meet performance and lifetime specifications. [0004] Apparatus with many different configurations are used to test IC devices. In many apparatus, such as the apparatus described in U.S. Pat. No. 6,323,666 to Ohba et al., the IC's are loaded into some sort of test board for environmental testing. Typically, the apparatus performs some initial electrical tests on the IC before subjecting the device to the environmental testing. That way, the more expensive, time consuming environmental test is only performed on ICs that pass the initial test. Other apparatus that describe apparatus the perform some electrical testing of ICs prior to environmental testing are described in U.S. Pat. No. 4,902,969 to Gussman and U.S. Pat. No. 6,563,331 to Maeng. [0005] Environmental testing is typically referred to as a burn-in test. The test is described as burn-in because it is done at an elevated temperature. Burn-in typically involves placing a large number of integrated circuit (IC) devices on printed circuit boards, referred to herein as test boards. The boards are placed in a chamber in which the environmental conditions, particularly temperature, are controlled. The IC devices are then subjected to electrical tests such as the application of DC current to forward and reverse bias the individual junctions in the IC or actively clocking the ICs to their maximum rated conditions. Running these tests at elevated temperature identifies ICs that do not perform according to their minimum specifications. [0006] There are two major objectives associated with such testing. The first and foremost objective is to ensure that ICs that fail or are likely to fail are discovered and kept from being used (at least in the application for which they were identified as likely to fail). The failed ICs, once identified, might be recycled, repaired, retested, etc. The second equally important objective is that the good ICs are not falsely identified as bad ICs. Such misclassification has a number of downsides. First, it wastes an otherwise good IC by preventing it from being used for its intended purpose. Second, a series of false failures can give the impression of an artificially high fail rate. This could lead to an unnecessary, expensive, and time-consuming search for the source or sources of the fail rate. [0007] Many apparatus have been proposed to more accurately identify failed ICs and to ensure that the ICs are not improperly identified as failures due to some defect or malfunction in the apparatus itself. One such approach is described in U.S. Pat. No. 6,323,666 to Ohba et al. With reference to FIG. 1, a test and burn-in system handler 10 is illustrated schematically. An electronic switch 4 is provided to switch between test signals of the IC test circuit 2 and the test signals of the burn-in board checker 3. The IC test circuit 2, the burn-in board checker 3 and the electrical switch 4 are made up as a unit. [0008] The IC test circuit 2 is used to perform a pretest of the IC's 1A as the devices under test. The burn-in board checker 3 is for testing the burn-in board 1 to detect pattern disconnection, solder failure, short circuits or other defects. The alignment stage 6 is used to straighten the attitude of the IC's 1A. [0009] The handler 10 is operated in the following manner. The carrier rack 8 has multiple burn-in boards 1, which, when loaded into the handler 10, do not contain IC devices. The burn-in boards 1, are inserted sequentially and each burn-in board, 1, is tested by the burn-in board checker 3 to determine if the burn-in board 1 contains any bad IC sockets. The burn-in board waits in this position to receive ICs 1A. [0010] The ICs are transferred one at a time from the tray 5 to the alignment stage 6. After the attitudes of the ICs are straightened at the alignment stage 6, the ICs 1A are populated into the burn-in board 1. If the burn-in board has a defective socket, the loading software is instructed not to populate that socket with an IC. [0011] After the burn-in board is loaded, the switch 4 is deployed to activate the IC test circuit 2. Simplified functional tests are performed on the ICs populating the burn-in board 1. After the electrical pretest, the ICs that are determined to be defective are removed from the burn-in board 1 while the devices that passed the pre-test remain. Once all of the normal sockets in the burn-in board 1 are loaded with ICs that were determined to be non-defective, the burn-in board is returned to the carrier rack 8. Once all of burn-in boards 1 in the carrier rack 8 are filled, the carrier rack is transferred to the burn-in apparatus. [0012] While the apparatus described above achieves some efficiency and accuracy by testing individual sockets in burn-in boards before loading ICs therein, greater efficiency and flexibility for such test apparatus are sought while still ensuring the IC failures are properly attributed to the IC device, and not actually the result of a bad burn-in board socket or other extraneous reason. SUMMARY OF THE INVENTION [0013] One aspect of the present invention provides an automated test handler system for testing integrated circuit devices prior to subjecting those devices to an environmental test. The test handler offers at least two modes of operation. In a first mode, individual integrated circuit (IC) devices under test (DUTs hereinafter) are electrically tested before they are placed in a test board. In a second mode, DUTs are electrically tested while in the test board. A test of DUTs when they are in the test board is referred to as a parallel test hereinafter. In yet a third mode, the DUTs are individually tested prior to being placed in the test board and are also subjected to a parallel test. [0014] The at least two modes of operation provide certain advantages over prior art methods and apparatus. In operation of the test handler system, according to this aspect of the present invention, the user can select between a mode where a high failure rate is expected (e.g. when new or prototype devices are being tested, the number of hard-failure devices is likely to be higher) and a mode where a lower failure rate is expected (e.g. devices that have been manufactured for some time). In the first mode, an individual electrical test is performed on DUTs before they are placed in the test board. This ensures that, if the DUTs do experience a hard-failure, the test of other DUTs will not be otherwise adversely affected (hard failure can pull down signal lines and stop test execution). Also, the individual electrical test can be performed if the test parameters require very tight tolerances or exacting test standards. As previously noted, in certain embodiments, the DUT will be subjected to both an individual electrical test and a parallel test. [0015] The test handler system of the present invention provides an advantageous flexibility in the testing of ICs. By providing two test stations, a parallel test station and an individual test station, the system is able to perform both sophisticated and exacting electrical tests on individual DUTs when required, yet can perform basic electrical tests on multiple DUTs simultaneously. By tracking the response of sockets to electrical tests (sockets can either be tested when empty using a probe-type device or when populated with a DUT as described in detail below) and linking the results of device tests to the sockets in which they were performed, the apparatus according to this aspect of the present invention can intelligently and more effectively manage the loading and unloading of test boards, and the testing of ICs, both individually and when populating sockets in test boards. [0016] The test handler system includes a handling apparatus that may consist of a unitary apparatus or as a set of apparatus that are operated in a coordinated fashion. The handling apparatus is used to manage the test and placement of DUTs. The test and handling apparatus typically has a single housing that ensures that the DUTs therein are kept in a sufficiently clean environment. Although the DUTs will be packaged, it is still desirable for the DUTs to be protected, as particles and moisture found in ambient conditions can adversely affect the DUTs. [0017] The handling apparatus desirably has a pick-and-place mechanism. The pick-and-place mechanism transports the DUTs from one location to another within the system. Pick-and-place mechanisms are robotic mechanisms that are well-known in the art, and will not be described in detail herein. Pick-and-place mechanisms are also known as suitable for transporting integrated circuit (IC) devices packaged using surface mount technologies (SMT) such as ball grid arrays (BGA) or chip scale package (CSP). While referred to as pick-and-place apparatus herein, the term is intended to encompass all mechanical methods for moving individual integrated circuit devices from one location to another. Also, while the term pick-and-place apparatus is used in the singular form, it is intended to include multiple apparatus that are operated in cooperation with each other. For example, one pick-and-place apparatus can be used to load a test board and a second apparatus can be used to unload the test board. However, because they are working in cooperation with each other to accomplish loading and unloading of test boards, they are referred to as a single apparatus. [0018] The handling apparatus also typically has a loader for loading test boards into the automated test handler system. In a preferred embodiment, the loader has a mechanism for storing a plurality of test boards in a storage cassette configuration. Such a configuration enables a plurality of empty test boards to be sequentially introduced into the apparatus. Once the test boards are populated with devices by the apparatus and those devices have been tested, the test board is returned to the storage cassette and another empty cassette is introduced into the system. This process is repeated until all devices have been tested or all cassettes are filled with completely populated test boards. [0019] The test boards have a plurality of sockets therein. The sockets are adapted to receive the DUTs. The test boards are configured to electrically interconnect the DUTs to test circuitry of the parallel tester. The test circuitry of the parallel tester is used to evaluate the performance of the DUTs under conditions designed to determine if the DUT is performing/will perform as desired. A number of such tests can be performed and the present invention is not limited to a particular electrical test. [0020] In addition to the parallel test described above, the test handler system is advantageously configured so that a DUT can be subjected to other, more rigorous electrical tests depending upon the needs of the manufacturer. These more rigorous electrical tests are referred to as individual device tests herein, because such tests, e.g. DC and/or parametric tests, require fully isolated test circuitry and therefore cannot be performed when the DUT is populated in a test board with other devices. Performing tests that require fully isolated test circuitry on devices populating sockets in a test board is tedious, as the devices need to be removed, tested and replaced one by one. Thus, subjecting DUTs to DC/Parametric tests when the DUTs are populating a test board would cause a significant delay in the testing process. [0021] The test system may be configured to conduct individual device tests concurrently with the in-board tests. That is, while one board is being tested (either loaded or empty) the individual device tests are being conducted on DUTs as they are placed into a second board. An individual DUT can be sequentially subjected to both the individual test (on its way from the input tray to the test board) and the parallel test (after being populated into a test board and the board is placed in the parallel tester). This is particularly advantageous if only some of the DUTs being tested require an individual test. In such a situation, the individual test can be conducted as part of the board loading process while another test board (populated with DUTs) is being tested in the parallel tester. Continue reading about Method for testing semiconductor devices and an apparatus therefor... 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