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Method for testing non-deterministic device dataRelated Patent Categories: Error Detection/correction And Fault Detection/recovery, Pulse Or Data Error Handling, Digital Logic TestingMethod for testing non-deterministic device data description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070214397, Method for testing non-deterministic device data. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This Application is a Continuation of application Ser. No. 10/606,848 filed on Jun. 26, 2003 incorporated herein by reference. FIELD OF THE INVENTION [0002] The invention relates generally to automatic test equipment, and more particularly to a method for enabling the testing of non-deterministic semiconductor device data. BACKGROUND OF THE INVENTION [0003] Test is an important step in the manufacture of semiconductor devices. The automatic test equipment (ATE), or testers, employed to carry out this task comprises sophisticated electronics capable of sending test signals to, and capturing output signals from, one or more devices under test (DUTs). ATE software often helps to orchestrate this back and forth flow of signals. [0004] Conventional testers, as shown in FIG. 1, feed tester data signals (drive data) originating from a pattern generator 12 to a device-under-test (DUT) 14 via interface circuitry commonly referred to as pin electronics 16. Response signals from the DUT are captured and compared to expected data with the resulting comparison data fed to a failure processor 18 in order to determine pass or fail conditions. The "expected" and "drive" data are typically programmed in the pattern generator vector memory (not shown) to occur at precise timings, in accordance with how the DUT should behave. If the data captured from the DUT fails to correspond with an expected condition, the device is considered to have failed that aspect of the test. [0005] Modern semiconductor devices are trending towards employing multiple processing cores on the same piece of silicon, or chip. Adding to this complexity is the overall trend towards implementing on-chip communication protocols including, for example, Rapid I/O, Hypertransport, and specialized bus architectures such as DDR and source synchronous, etc. The end result is an exponential increase in the chip gate count, yet only modest increases in the available pin counts. Consequently, multiple sub-circuits often share the pins (interface). [0006] This shared interface scheme is illustrated generally in FIG. 2, where a plurality of device-under-test subcircuits 20a-20c send data packets to a DUT communications port 22. The communications port serves as the gatekeeper to accessing the DUT output pin 24. Each of the subcircuits may be clocked by a separate clock having a frequency different from not only the other subcircuits, but also possibly different from the communications port clock. An asynchronous arbitrator 26 handles the sequencing of the data packets to the DUT output pin. [0007] During typical DUT operation, as shown in FIG. 3, the shared interface scheme may cause a problem (for conventional ATE) known as "out-of-order data". This situation often results from the subcircuits attempting to access the communications port 22 (FIG. 2) on the same clock edge, or having differing delays due to environmental conditions. FIG. 3 illustrates the general concept on how an expected sequencing may be disturbed into an out-of-order packet sequence. The "out of order" data problem presents a unique challenge to automatic test equipment, which is conventionally dependent on deterministic data from the DUT. [0008] What is desired and currently unavailable is a test solution for non-deterministic data that provides substantially real-time validation results and maximizes flexibility for the device manufacturer while reducing test costs. The apparatus and method of the present invention provides such a solution. SUMMARY OF THE INVENTION [0009] The present invention provides the ability for automatic test equipment to quickly validate non-deterministic data, such as "out of order" data received from a device-under-test. This ability is available with little to no impact to the automatic test equipment hardware, and is universally applicable to many protocols. With the availability of such a solution, users of the automatic test equipment will experience significant test throughput improvements and reduced test costs. [0010] To realize the foregoing advantages, the invention in one form comprises a method for testing semiconductor devices that output non-deterministic entity information such as packet and control signals. The method includes the steps generating test signals with a semiconductor tester and applying the generated test signals to the device-under-test. Actual output entities from the DUT in response to the applied generated test signals are captured by the tester and compared to expected output entities. If a failure is identified in the comparing step, the method defines a window of valid expected entities and compares the failed actual output entity to the window of valid expected entities. If a match occurs between the failed actual output entity and any of the expected entities in the window, the actual entity is deemed valid. [0011] Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0012] The invention will be better understood by reference to the following more detailed description and accompanying drawings in which [0013] FIG. 1 is a high-level block diagram of a conventional ATE architecture for driving data to a DUT and comparing the DUT response data to expected data; [0014] FIG. 2 is a high-level block diagram of a DUT output interface architecture; [0015] FIG. 3 is a block diagram illustrating the out of order problem resulting from the DUT output scheme of FIG. 2; [0016] FIG. 4 is an elevated perspective view of a semiconductor tester employing the method of the present invention; [0017] FIG. 5 is a flowchart illustrating steps included in one form of the present invention; [0018] FIG. 6 is a flowchart illustrating more specific steps for the compare step of FIG. 5; and [0019] FIG. 7 is a graphical representation of a valid entity window in accordance with the method shown in FIG. 5. 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