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Method for reducing cross-talk induced source synchronous bus clock jitter

The present invention relates in general to off-chip transmission line drivers and receivers, and in particular, to methods for reducing transition induced cross-talk edge jitter in source synchronous clock systems.

Digital computer systems have a history of continually increasing the speed of the processors used in the system. As computer systems have migrated towards multiprocessor systems, sharing information between processors and memory systems has also generated a requirement for increased speed for the off-chip communication networks. Designers usually have more control over on-chip communication paths than for off-chip communication paths. Off-chip communication paths are longer, have higher noise, impedance mismatches, and have more discontinuities than on-chip communication paths. Since off-chip communication paths are of lower impedance, they require more current and thus more power to drive.

When using inter-chip high-speed signaling, noise and coupling between signal lines (crosstalk) affects signal quality. One way to alleviate the detrimental effects of noise and coupling is through the use of differential signaling. Differential signaling comprises sending a signal and its complement to a differential receiver. In this manner, noise and coupling affect both the signal and the complement equally. The differential receiver only senses the difference between the signal and its complement as the noise and coupling represent common mode signals. Therefore, differential signaling is resistant to the effects that noise and crosstalk have on signal quality. On the negative side, differential signaling increases pin count by a factor of two for each data line. The next best thing to differential signaling is pseudo-differential signaling. Pseudo-differential signaling comprises comparing a data signal to a reference voltage using a differential receiver or comparator.

When high speed data is transmitted between chips, the signal lines are characterized by their transmission line parameters. High speed signals are subject to reflections if the transmission lines are not terminated in an impedance that matches the transmission line characteristic impedance. Reflections may propagate back and forth between driver and receiver and reduce the margins when detecting signals at the receiver. Some form of termination is therefore usually required for all high-speed signals to control overshoot, undershoot, and increase signal quality. Typically, a Thevenins resistance (equivalent resistance of the Thevenins network equals characteristic impedance of transmission line) is used to terminate data lines allowing the use of higher valued resistors. Additionally, the Thevenins network is used to establish a bias voltage between the power supply rails. In this configuration, the data signals will then swing around this Thevenins equivalent bias voltage. When this method is used to terminate data signal lines, a reference voltage is necessary to bias a differential receiver that operates as a pseudo-differential receiver to detect data signals in the presence of noise and crosstalk.

The logic levels of driver side signals are determined by the positive and ground voltage potentials of the driver power supply. If the driver power supply has voltage variations that are unregulated, then the logic one and logic zero levels of the driver side signals will undergo similar variations. If the receiver is substantially remote from the driver such that its power supply voltage may undergo different variations from the driver side power supply, then additional variations will be added to any signal received in a receiver side terminator (e.g., Thevenins network). These power supply variations will reduce noise margins if the reference has variations different from those on the received signals caused by the driver and receiver side power supply variations.

The popular technique of source-synchronous clocking is often used for high speed interface systems. With this technique, the transmitting device sends a clock with the data. The advantage of this approach is that the maximum performance is no longer computed from the clock-to-output delay, propagation delay, and set up times of the devices and the circuit board. Instead, the maximum performance is related to the maximum edge rate of the driver and the skew between the data signals and the clock signals. Using this technique, data may be transferred at a 1 Gbps rate (1-nsec bit period) even though the propagation delay from transmitter to receiver may exceed one nanosecond. If standard double-data rate (DDR) driving is utilized, data is launched on both the rising and falling edges of the clock. In this case, duty cycle symmetry of the clock as detected at the receiver becomes important since each edge of the clock is also used to recover the data at the receiving end of the data path. If the clock is asymmetrical, then it will affect the eye pattern of the data signals that the clock is used to detect.

In high speed data transmission across a densely routed multi-chip module (MCM) package, the clock and data signals may be experience considerable coupling between parallel lines. This noise coupling reduces the fidelity of the data signals and adds edge jitter to the clock signals. These factors may limit the data rate of the chip to chip interfaces. In order to transmit error-free data across the chip to chip interface, either the signaling rate or the amount of coupling between signaling lines must be reduced. Reducing data rate is usually not desirable since it reduces the ability of the system to meet performance targets. Therefore, to maintain an acceptable data rate the coupled noise must be reduced for error-free operation.

Typical methods of cross-talk reduction including introducing “shield” traces between signals in the package or adding more space between the signal lines. This approach are less than optimal because it forces the reduction in the number of usable signals that may be routed between chips thereby again compromising the ability of the system to meet bandwidth targets. These methods fail in part because the decrease in coupled noise does not warrant the increase in expensive MCM area required.

Of particular concern, is noise coupled to the clock edges when a source synchronous clock is launched in phase with its associated data. In this case, there is opportunity for data transitions to interact with clock edge transitions over the interface path resulting in clock edge jitter. Clock edge jitter will adversely affect the eye pattern for all data signals clocked with the received source clock. The received source clock and data signals will be aligned at the receiving chip but the clock edge jitter will remain causing a degradation in margins affecting error rates.

There is, therefore, a need for a method of reducing coupling between the edge transitions of a source clock signal and adjacent synchronous data signals.

In a source synchronous interface, the clock and data signals are launched simultaneously from a driving chip to a receiving chip. There may be a large number of closely spaced signals lines on a multi-chip module containing several IC chips that are coupled with communication buses. One type of cross-talk occurs when an aggressor data signal switches and couples switching noise onto an adjacent clock signal. Since the data and clock edges are aligned, the coupled noise will affect edges of the clock signal resulting in the clock edges being shifted forward or backward depending whether the coupling occurs on a rising or falling edge of the data signal.

Embodiments of the present invention purposely shift the propagating clock signal one-half clock cycle of the source clock that generates the data signal edges at each same polarity source clock edge. Thus the propagating clock is purposely shifted one-fourth of its clock cycle relative to the data signal edges. In this manner, noise coupled from propagating data signals to propagating clock signals only occur during either the logic one or logic zero clock state and not when the propagating clock is transitioning between logic states. When the propagating clock is received at the receiver chip, it is re-aligned with the data signals before it is used to sample the received data. The cross-talk induced jitter in the propagating clock is reduced resulting in higher reliability communication between IC chips.

In one embodiment, a select signal may be used to propagate either the shifted or un-shifted clock signal. A variety of circuits may be used to generate the delayed or shifted clock signal.

A main clock of frequency F is used to launch data signals such that data transitions occur synchronous with the one edge of the source clock. A source clock with a frequency F/2 is generated from the main clock. A propagating clock is coupled to an off-chip driver by clocking the source clock with the main clock such that the propagating clock is shifted one-half cycle of the main clock. The propagating clock has edge transitions that occur half way between data transitions of an alternating one/zero logic pattern. In this manner, any coupling between the propagating clock and an adjacent data signal will occur at static logic levels of either signal. Since coupling does not occur during edges of the propagating clock signal, its edge jitter is reduce thereby improving the eye diagram of received data clocked by the received propagating clock signal.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: