| Method for preparing a metal feature surface prior to electroless metal deposition -> Monitor Keywords |
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Method for preparing a metal feature surface prior to electroless metal depositionRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects), Diverse Conductors, Having Refractory Group Metal (i.e., Titanium (ti), Zirconium (zr), Hafnium (hf), Vanadium (v), Niobium (nb), Tantalum (ta), Chromium (cr), Molybdenum (mo), Tungsten (w), Or Alloy Thereof)Method for preparing a metal feature surface prior to electroless metal deposition description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070184652, Method for preparing a metal feature surface prior to electroless metal deposition. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD OF THE INVENTION [0001] The present invention is directed, in general, to a method for preparing a metal feature and, more specifically, to a method for preparing a metal feature surface prior to electroless metal deposition. BACKGROUND OF THE INVENTION [0002] The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors. [0003] The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device should be smaller without damaging the operating characteristics thereof. High packing density, low heat generation, and low power consumption, with good reliability and long operation life must be maintained without any functional device degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size. [0004] As integrated circuits become denser, the widths of interconnect layers that connect transistors and other semiconductor devices of the integrated circuit are reduced. As the widths of interconnect layers and semiconductor devices decrease, their resistance increases. Accordingly, semiconductor manufacturers seek to create smaller and faster devices by using, for example, a copper interconnect instead of a traditional aluminum interconnect. Unfortunately, copper is very difficult to etch in most semiconductor process flows. Therefore, damascene processes have been proposed and implemented to form copper interconnects. [0005] Damascene methods usually involve forming a trench and/or an opening in a dielectric layer that lies beneath and on either side of the copper-containing structures. Once the trenches or openings are formed, a blanket layer of the copper-containing material is formed over the entire device. Electrochemical deposition (ECD) is typically the only practical method to form a blanket layer of copper. The thickness of such a layer must be at least as thick as the deepest trench or opening. After the trenches or openings are filled with the copper-containing material, the copper-containing material over them is removed, e.g., by chemical-mechanical polishing (CMP), so as to leave the copper-containing material in the trenches and openings (e.g., forming an interconnect) but not over the dielectric or over the uppermost portion of the trench or opening. [0006] After forming the copper interconnect, a capping layer may be formed thereover. The capping layer is designed to act as a diffusion barrier between the copper in the interconnect and other features located thereby, as well as an etch stop layer for subsequent interconnects. Electroless cobalt plating may be used to selectively deposit a cobalt alloy capping layer on top of the copper interconnect after CMP. This process is catalyzed by the copper interconnect surface, which allows the cobalt alloy capping layer to selectively deposit on the copper interconnect (e.g., it does not deposit on the surrounding dielectric). [0007] The electroless cobalt plating, however, currently has certain drawbacks. One such drawback is the lack of coverage of the copper interconnect that results after the electroless cobalt plating. This lack of coverage may, and often will, negatively affect the electrical performance of the interconnect. Other problems may also result. [0008] Accordingly, what is needed in the art is a method for manufacturing an interconnect that does not experience the aforementioned problems of the prior art. SUMMARY OF THE INVENTION [0009] To address the above-discussed deficiencies of the prior art, the present invention provides a method for manufacturing an interconnect and an integrated circuit. The method for manufacturing the interconnect, in one embodiment, includes forming a first metal feature over or within a substrate, subjecting the first metal feature to a hydrogen containing plasma, the hydrogen containing plasma configured to remove organic residue from an exposed surface of the first metal feature, and electroless depositing a second metal feature on the first metal feature having been subjected to the hydrogen containing plasma. The method for manufacturing the integrated circuit, in addition to the formation of the interconnect, includes forming one or more transistors over a substrate, the interconnect configured to connect the one or more transistors and form an operational integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS [0010] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [0011] FIGS. 1-5 illustrate sectional views of detailed manufacturing steps instructing how one might, in an advantageous embodiment, manufacture an interconnect structure in accordance with the principles of the present invention; and [0012] FIG. 6 illustrates a sectional view of an integrated circuit (IC) incorporating interconnect structures constructed according to the principles of the present invention. DETAILED DESCRIPTION [0013] The present invention is based, at least in part, on the acknowledgement that organic residue on an upper surface of a metal feature may inhibit the electroless metal deposition of a second metal feature thereon. Having made this acknowledgement, the present invention further acknowledges that conventional wet cleans are ineffective at removing the organic residue without extreme damage to the metal feature. Based upon the aforementioned recognitions, as well as substantial experimentation, the present invention recognizes that a hydrogen containing plasma could be used to remove a substantial portion, if not all, of the organic residue from the metal feature prior to the electroless metal deposition of the second metal feature. The present invention further recognizes that the hydrogen containing plasma can be conducted without severe damage to the metal feature. [0014] Turning now to FIGS. 1-5, illustrated are sectional views of detailed manufacturing steps instructing how one might, in an advantageous embodiment, manufacture an interconnect structure in accordance with the principles of the present invention. FIG. 1 illustrates an interconnect structure 100 at an initial stage of manufacture. The interconnect structure 100 illustrated in FIG. 1 includes a dielectric layer 110, such as an interlevel dielectric layer located over a gate structure. The dielectric layer 110 may comprise any dielectric material known by those skilled in the art, such as silicon dioxide, a low dielectric constant material, or a non-silicon dielectric material. Located within the dielectric layer 110 is an opening 115. One skilled in the art understands how to form such an opening 115, including conducting conventional lithographic and etching techniques on a blanket layer of dielectric material. [0015] Conventionally formed within the opening 115 in the embodiment shown are a barrier layer 120 and seed layer 130. In the illustrative embodiment shown, the barrier layer 120 and seed layer 130 are also formed over an upper surface of the dielectric layer 110. As those skilled in the art appreciate, the barrier layer 120 is configured to substantially reduce, if not prevent, a metal located within the opening 115 in the dielectric layer 110 from diffusing into nearby structures. Similarly, as those skilled in the art appreciate, the seed layer 130 is configured to provide a surface upon which a subsequent metal layer can easily be deposited. [0016] The materials chosen for the barrier layer 120 and seed layer 130 are generally dependent on the particular material being used for the first metal layer 210 (FIG. 2). In the given embodiment, however, the first metal layer 210 (FIG. 2) comprises copper, and thus the barrier layer 120 might comprise tantalum, tantalum nitride, Tungsten alloys, Ruthenium or ruthenium alloys, and the seed layer 130 might comprise a copper or copper alloy seed layer. It goes without saying that these materials would most likely change if the first metal layer 210 (FIG. 2) were to comprise a different material, for instance tungsten. Accordingly, the present invention should not be limited to any specific material. [0017] Turning now to FIG. 2, illustrated is a sectional view of the interconnect structure 100 of FIG. 1, after formation of a first metal layer 210 over the barrier layer 120 and seed layer 130, as well as within the opening 115. In the illustrative embodiment of FIG. 2 the first metal layer 210 is formed to an appropriate thickness (t.sub.1) to fill the opening 115, thus the first metal layer 210 is also formed over an upper surface of the dielectric layer 110. [0018] In the illustrative embodiment shown in FIG. 2, the first metal layer 210 comprises copper, however, those skilled in the art appreciate that other similar materials that are currently known or hereafter discovered may comprise the first metal layer 210. In the particular embodiment where the first metal layer 210 comprises copper, the first metal layer 210 may be formed using a conventional electroplating process. As this process is conventional, no further detail will be given. Were the first metal layer 210 to comprise a different material than copper, an appropriate formation technique would be used to form this different material. [0019] Turning to FIG. 3, illustrated is a sectional view of the interconnect structure 100 illustrated in FIG. 2, after polishing the first metal layer 210, seed layer 130 and barrier layer 120 from the top surface of the dielectric layer 110, resulting in a first metal feature 310 having a lesser thickness (t.sub.2). Those skilled in the art understand the conventional processes that may be used to polish the first metal layer 210, seed layer 130 and barrier layer 120. In the embodiment shown, however, a conventional chemical-mechanical polishing (CMP) process is used. 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