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10/04/07 | 33 views | #20070232209 | Prev - Next | USPTO Class 451 | About this Page  451 rss/xml feed  monitor keywords

Method for polishing a semiconductor wafer

USPTO Application #: 20070232209
Title: Method for polishing a semiconductor wafer
Abstract: An apparatus for polishing a wafer comprises a supporting portion having an abrasive pad disposed thereon, and a polishing head disposed over the abrasive pad. The polishing head comprises a carrier having at least two fluid passages, a retainer ring disposed on a lower edge of the carrier, forming a space for receiving the wafer, a supporter disposed in the carrier, and a flexible membrane disposed to be in contact with the wafer. The supporter has an upper surface portion, a lower surface portion, a plurality of first holes, a plurality of second holes, and a first chamber. The upper surface portion of the supporter forms a second chamber along with an inner surface of the carrier. The second chamber is in communication with one of the two fluid passages of the carrier and the second holes are formed in a lower surface portion of the supporter to communicate with the second chamber. The first chamber is in communication with the other one of the two fluid passages and the first holes are formed in the lower surface portion of the supporter to communicate with the first chamber. The lower surface portion of the supporter has a flat surface and a chamfered or rounded edge. The membrane disposed to enclose the lower surface portion of the supporter has a plurality of third holes formed at positions corresponding to the first holes to absorb and hold the wafer by vacuum.
(end of abstract)
Agent: Mills & Onello LLP - Boston, MA, US
Inventors: Jae-Phil Boo, Jun-Gyu Ryu, Sang-Seon Lee, Sun-Wung Lee
USPTO Applicaton #: 20070232209 - Class: 451388000 (USPTO)
Related Patent Categories: Abrading, Work Holder, Vacuum

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