| Method for patterning hfo2-containing dielectric -> Monitor Keywords |
|
|
  Method for patterning hfo2-containing dielectricUSPTO Application #: 20060019452Title: Method for patterning hfo2-containing dielectric Abstract: A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas plasma is provided to remove portions of the HfO2-containing gate dielectric. (end of abstract) Agent: North America Intellectual Property Corporation - Merrifield, VA, US Inventors: Jeng-Huey Hwang, Wei-Tsun Shiau, Chien-Ting Lin, Jiunn-Ren Hwang USPTO Applicaton #: 20060019452 - Class: 438287000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Gate Insulator Structure Constructed Of Diverse Dielectrics (e.g., Mnos, Etc.) Or Of Nonsilicon Compound The Patent Description & Claims data below is from USPTO Patent Application 20060019452. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of application Ser. No. 10/710,581 filed Jul. 22, 2004. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to a method for patterning an HfO2-containing dielectric, and more particularly, to a method for patterning an HfO2-containing gate dielectric without damaging STI positioned on the same wafer. [0004] 2. Description of the Prior Art [0005] For realizing the low power MOS transistor at the 65 nm node and beyond, it is necessary to reduce the gate leakage current for thinner gate dielectrics. The introduction of high-k gate material would be advantageous for extending current MOS technology. After several years of work, many research groups are now focusing on hafnium (Hf) based material and are evaluating the natural of these materials extensively. Among the considerable Hf-based materials, HfO2 is often evaluated to be combined into a metal gate structure. [0006] However, HfO2-containing dielectric (including HfO2, HfSiO, HfSiON, HfAlO, and so on) is known for more difficult to be pattern etched comparing to SiO2 based dielectric. The conventional method of etching the HfO2-containing dielectric involves using a strong acid, such as 49% HF solution. When using the 49% HF solution to etch the HfO2-containing dielectric, a SiO2 layer, such as a shallow trench isolation (STI) layer, will be also removed. Furthermore, the etching rate of the SiO2 layer is much higher than that of the HfO2-containing dielectric, and the SiO2 layer will be seriously damaged while patterning the HfO2-containing dielectric. [0007] Another conventional method of etching the HfO2-containing dielectric is using a high insert gas plasma with more than 60% Ar. The insert gas plasma has no selectivity while etching, and may also result in the SiO2 layer being damaged during over-etch. [0008] Please refer to FIGS. 1 and 2, which show a conventional etching process of the HfO2-containing dielectric. An STI layer 18 is formed on a wafer 10, and an HfO2-containing gate dielectric 12 covers the wafer 10 and the STI layer 18. A gate electrode 16 is formed on the HfO2-containing gate dielectric 12, and two spacers 14 are formed beside the gate electrode 16. As shown in FIG. 2, the conventional etching process such as using the strong acid or the insert gas plasma is performed to remove portions of the HfO2-containing gate dielectric 12. The etching selectively between the HfO2-containing gate dielectric 12 and the STI layer 18 is too low to bring serious damages atop the STI layer 18. As a result, the isolation effect of the STI layer 18 is reduced. SUMMARY OF THE INVENTION [0009] It is therefore a primary objective of the claimed invention to provide a method for patterning the HfO2-containing gate dielectric without damaging the SiO2 layer to solve the above-mentioned problem. [0010] According to the claimed invention, a method for patterning an HfO2-containing gate dielectric comprises providing a wafer having a trench, a STI layer formed in the trench, the HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. Following that, the wafer is preheated and a bromine-rich gas plasma is provided to remove portions of the HfO2-containing gate dielectric. [0011] According to the claimed invention, a method for patterning an HfO2-containing gate dielectric comprises providing a wafer having a trench, a STI layer formed in the trench, the HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. Following that, a nitrogen ion bombardment is used to convert the exposed HfO2-containing gate dielectric to a Hf3N4 layer. A phosphoric acid is used to remove the Hf3N4 layer. [0012] It is an advantage of the claimed invention that the bromine-rich gas plasma has a high selectivity between the HfO2-containing dielectric and the SiO2 layer, so that the HfO2-containing dielectric can be etched without damaging the SiO2 layer. [0013] It is another advantage of the claimed invention that the nitrogen ion bombardment can convert the HfO2-containing dielectric to the Hf3N4 layer and the phosphoric acid has a high selectivity between the Hf3N4 and SiO2 layers, so that the HfO2-containing dielectric can be etched without damaging the SiO2 layers. [0014] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0015] FIG. 1 is a schematic diagram of a wafer before performing a gate dielectric patterning process thereon according to the prior art; [0016] FIG. 2 is a schematic diagram of a wafer after performing a gate dielectric patterning process thereon according to the prior art; [0017] FIG. 3 is a schematic diagram of a wafer after performing a gate dielectric patterning process thereon according to the present invention; and [0018] FIG. 4 is a schematic diagram of a wafer after performing a gate dielectric patterning process thereon according to a second embodiment of the present invention. DETAILED DESCRIPTION [0019] Please refer to FIG. 3, which shows a result of performing a patterning process according to a first embodiment of the present invention. In the first embodiment of the present invention, a bromine-rich gas plasma is utilized to accomplish the requirement of etching the HfO2-containing dielectric with a high selectivity. In this embodiment, a MOS transistor fabrication is used to explain the present invention. Before the etching process, the half-manufactured wafer is similar to that of the prior art as shown in FIG. 1. For example, the STI layer 18 is formed on the wafer 10, and the HfO2-containing gate dielectric 12 covers the wafer 10 and the STI layer 18. The gate electrode 16 is formed on the HfO2-containing gate dielectric 12, and two spacers 14 are formed beside the gate electrode 16. The STI layer 18 and the spacer 14 may be formed of SiO2, and the gate electrode 16 may be formed of TaN or TiN. Continue reading... Full patent description for Method for patterning hfo2-containing dielectric Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method for patterning hfo2-containing dielectric patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method for patterning hfo2-containing dielectric or other areas of interest. ### Previous Patent Application: Method for patterning hfo2-containing dielectric Next Patent Application: Nrom flash memory with a high-permittivity gate dielectric Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Method for patterning hfo2-containing dielectric patent info. IP-related news and info Results in 2.78742 seconds Other interesting Feshpatents.com categories: Medical: Surgery , Surgery(2) , Surgery(3) , Drug , Drug(2) , Prosthesis , Dentistry |
||
