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Method for measuring interface traps in thin gate oxide mosfetsMethod for measuring interface traps in thin gate oxide mosfets description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080096292, Method for measuring interface traps in thin gate oxide mosfets. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001]The present invention relates to interface traps within MOSFETs, and in particular to a method for measuring interface traps in thin gate oxide MOSFETs. BACKGROUND OF THE INVENTION [0002]As is known in the art, semiconductor wafers often contain material interfaces such as between silicon and silicon dioxide. Contaminants and other defects at the oxide silicon interface can cause problems in the manufacture and performance of integrated circuits that are fabricated over that interface. These defects, often referred to as interface traps, are capable of trapping and de-trapping charge carriers. Interface traps can have an adverse effect on device performance, for example, an interface trap can cause discrete switching in the source conductance, band-to-band tunneling (BBT) of hot carriers from the gate-to-drain which can result in gate-induced drain leakage current, drain current fluctuation, voltage drop in the gate area, threshold voltage shift in the MOS transistors, and the like. [0003]For example, impurities such as contaminants, metals, and the like, are often introduced at the oxide layer/semiconductor interface during oxidation processing, plasma deposition, etching or other processing steps. There is a need to determine the quality of these interfaces prior to or during the manufacture of semiconductor devices on the wafer. Interface trap charge pumping is a well-known transient recombination effect that is activated by cycling or pumping the Si--SiO.sub.2 interface of the MOSFET between accumulation and inversion states. Charge-pumping measurements can then be used to extract or determine interface trap density, and the effect of gate leakage can be compensated for by measuring charge-pumping current at a low frequency, for example, and then subtracting it from measurement results at higher frequencies. [0004]Basic charge-pumping techniques involve measuring the substrate output current while applying input voltage pulses of fixed amplitude, rise time, fall time, and frequency to the gate of the transistor, with the source, drain, and body tied to ground, for example. The electrical pulse can be applied with a fixed amplitude, a voltage base sweep, a fixed base, a variable amplitude sweep, and the like. The charge pumping method can evaluate the surface states at the silicon (Si)--silicon dioxide (SiO.sub.2) interface of MOSFET devices, for example. [0005]The traditional charge pumping technique for characterizing interface traps fails when tunneling current is comparable to or greater than the charge pumping current, as it is difficult to separate the two currents. A-priori estimation of the average gate tunneling current (which is a function of the gate voltage waveform) into the bulk or source/drain of the MOSFET during charge pumping leads to inaccuracies due to the exponential dependence of gate tunneling current on the gate voltage. [0006]FIG. 1 is a prior art technique setup at 100, illustrating the application of a square or trapezoidal pulse wave, utilizing a pulse generator 102, to a gate 104 of a metal oxide semiconductor field effect transistor (MOSFET) 106 that overlies a thin gate oxide 108. It should be appreciated by one of ordinary skill in the art that the pulse wave can be square or trapezoidal or a linear combination of both. In addition, the pulse wave can be triangular, sinusoidal, rectangular, comb, and the like. As illustrated, a source 110 and drain 112 are both shorted and grounded while measuring the current output at a current measuring device 114. As a positive or negative bias is applied to the gate 104, the surface of the MOSFET accumulates or inverts, respectively, and if there are interface traps located at the gate oxide, bulk substrate interface, the traps will tend to go back to either the conduction band or the valence band, depending on the type of traps present. By pulsating the interface traps rapidly, the technique takes advantage of the fact that traps have only a finite response time, therefore only some of the traps will go back to the conduction or valence band. However, some of the traps will remain "trapped" and recombine with the inversion charge or the accumulation charge coming from the bulk. [0007]There is a substantial current measurement difference between devices, when evaluating an enhanced complementary metal oxide semiconductor (CMOS) as opposed to a MOSFET where they gate dielectric is very thin. Utilizing a thin gate dielectric, if there is an increase in the voltage beyond inversion, or if the device is taken to deep accumulation, that results in a significant amount of gate current. However, this gate current is small, when compared to a normal MOSFET operating current, which is the source/drain current. The current measured is a very small current, many orders of magnitude lower than the normal device current. In an advanced CMOS device, the magnitude of the tunneling current approaches and often exceeds the magnitude of the charge pumping current for the density of interface traps of interest. These values can range from tens to hundreds of picoamps per square micron. [0008]Thus, there is a need to provide a method for measuring interface traps in thin gate oxide MOSFETs that overcomes the previously mentioned problems. SUMMARY OF THE INVENTION [0009]The present invention is directed to a method for determining charge pumping current to determine the number of interface traps present in a MOSFET. In accordance with one aspect of the present invention, the method comprises plotting charge pumping current versus frequency. The method further comprises determining the number of interface traps participating in the charge pumping current based upon the slope of the plot. In addition, the tunneling current can be determined based upon the y-intercept of the plot for a given duty cycle. [0010]Two key observations that were made according to an aspect of the invention are that the charge pumping current only occurs at V.sub.hi to V.sub.lo or V.sub.lo to V.sub.hi transitions. In addition, for example, the gate tunneling current to the source/drain or substrate depends only on the duty cycle and not the frequency of the gate pulses, to the first order. The method thus provides a way to separate charge pumping current from tunneling current when tunneling current for the MOSFET is greater than or equal to the charge pumping current. [0011]Additionally, according to another aspect of the invention, the method provides a way to determine the errors in those calculations and plots as well as to validation of those measurements. [0012]To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0013]FIG. 1 is a block diagram of a prior art set up used for conventional charge pumping; [0014]FIG. 2 is a trapezoidal wave pulse utilized in the charge pumping, in accordance with one aspect of the present invention; [0015]FIG. 3A illustrates a trapezoidal charge pumping wave in accordance with yet another aspect of the present invention; [0016]FIG. 3B illustrates yet another trapezoidal charge pumping wave at a different frequency than in FIG. 3A, in accordance with another aspect of the present invention; [0017]FIG. 4 is a graphical representation of substrate current versus frequency according to another aspect of the present invention; [0018]FIG. 5 illustrates an experimental result according to one aspect of the present invention; [0019]FIG. 6 illustrates another experimental result according to one aspect of the present invention; [0020]FIG. 7 illustrates measurements on various devices according to other aspects of the present invention; Continue reading about Method for measuring interface traps in thin gate oxide mosfets... Full patent description for Method for measuring interface traps in thin gate oxide mosfets Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method for measuring interface traps in thin gate oxide mosfets patent application. Patent Applications in related categories: 20090298205 - Pattern verifying method, pattern verifying device, program, and manufacturing method of semiconductor device - An overlapping margin of a second pattern for a first pattern is corrected for at least one of the first pattern and the second pattern (S50). Next, a relative distance between the first pattern and the second pattern after the overlapping margin is corrected is calculated (S60). Next, it is ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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