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10/19/06 - USPTO Class 438 |  11 views | #20060234408 | Prev - Next | About this Page  438 rss/xml feed  monitor keywords

Method for manufacturing vertical group iii-nitride light emitting device

USPTO Application #: 20060234408
Title: Method for manufacturing vertical group iii-nitride light emitting device
Abstract: The invention provides a vertical group III-nitride light emitting device improved in external extraction efficiency and a method for manufacturing the same. The method includes forming an undoped GaN layer and an insulating layer on a basic substrate. Then, the insulating layer is selectively etched to form an insulating pattern, and an n-doped AlxGayIn(1-x-y)N layer, an active layer and a p-doped AlmGanIn(1-m-n)N layer are sequentially formed on the insulating pattern. A conductive substrate is formed on the p-doped AlmGanIn(1-m-n)N layer. The basic substrate, the undoped gaN layer and the insulating pattern are removed, and an n-electrode is formed on a part of the exposed surface of the n-doped AlxGayIn(1-x-y)N layer. (end of abstract)



Agent: Mcdermott Will & Emery LLP - Washington, DC, US
Inventors: Jae Hoon Lee, Yong Chun Kim, Hyung Ky Back, Moon Heon Kong, Dong Woo Kim
USPTO Applicaton #: 20060234408 - Class: 438022000 (USPTO)

Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Device Or Circuit Emissive Of Nonelectrical Signal

Method for manufacturing vertical group iii-nitride light emitting device description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20060234408, Method for manufacturing vertical group iii-nitride light emitting device.

Brief Patent Description - Full Patent Description - Patent Application Claims
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CLAIM OF PRIORITY

[0001] This application claims the benefit of Korean Patent Application No. 2004-31107 filed on Apr. 14, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a method for manufacturing a group III-nitride light emitting device, and more particularly, a method for manufacturing a vertical group III-nitride light emitting device improved in external extraction efficiency.

[0004] 2. Description of the Related Art

[0005] Since development of a light emitting diode (LED) including a group III-nitride semiconductor, it has been utilized as a light source in a variety of areas such as a liquid crystal display (LCD) backlight, a mobile phone keypad, a illumination lighting source and the like. Regarding development of the LED for wide-ranging purposes, light-emitting efficiency and heat releasing properties thereof have emerged as a significant factor. Light-emitting efficiency of the LED is determined by light generation efficiency, extraction efficiency and amplification efficiency by fluorescent material. Most of all, the biggest problem concerns low extraction efficiency, that is, light generated is externally extracted at a low efficiency. The greatest hurdle against light extraction out of the LED is extinction of light resulting from total internal reflection. That is, big refractivity differences at an interface of the LED allows only about 20% of light generated to exit outside the interface of the LED. The light totally reflected at the interface travels inside the LED and is reduced to heat. This increases a heat release rate of the LED, and decreases external extraction efficiency of the LED, thus shortening lifetime thereof.

[0006] To overcome this problem, suggestions have been made regarding methods for improving external extraction efficiency. For example, a surface pattern or a surface texture is formed on the LED to enable a photon arriving at its surface to scatter randomly. Alternatively, the light emitting device is shaped as a truncated inverted pyramid. Furthermore, in another recent method, to form a photonic crystal, the LED surface is patterned such that a photon of a specified wavelength is transmitted or reflected selectively. "High-Extraction-Efficiency Blue Light-Emitting Diode Using Extended-Pitch Photonic Crystal" by Kenji Orita et al., Japanese Journal of Applied Physics, Vol. 43, No. 8B, 2004, pp. 5809-5813 discloses such a method in which a p-doped cladding layer is selectively dry etched to form rough patterns of photonic crystal on the upper surface of the cladding layer.

[0007] FIG. 1 is a sectional view illustrating a conventional group III-nitride light emitting device having a photonic crystal on the upper surface thereof. With reference to FIG. 1, the conventional group III-nitride light emitting device 10 includes an n-doped GaN cladding layer 13, an active layer 15, a p-doped GaN cladding layer 17 sequentially formed on a sapphire substrate 11. On one side of the p-doped GaN cladding layer 17, a p-electrode 21 is formed, and on the upper surface of the n-doped GaN cladding layer 13 which is exposed via mesa etching, an n-electrode 23 is formed. In addition, a transparent electrode layer 19 is formed on the p-doped GaN cladding layer 17. As shown in FIG. 1, a rough pattern 25 of photonic crystal is formed on the upper surface of the p-doped GaN cladding layer 17. The rough pattern 25 functions to increase the extraction efficiency of the light emitting device. That is, the light incident on the rough pattern 25 is effectively extracted out of the light emitting device via scattering and diffraction.

[0008] In order to form such a rough pattern 25 of photonic crystal, a metal mask is formed via electron-beam lithography and the p-doped GaN cladding layer is selectively etched via Reactive Ion Etching (RIE). That is, after a nickel film (not shown) is deposited on the p-doped GaN cladding layer 17, the nickel film is patterned via electron-beam lithography to form a nickel pattern. This nickel pattern is used as an etching mask to dry-etch the p-doped GaN cladding layer 17 via RIE, thereby forming a rough pattern 25 of photonic crystal on the upper surface of the p-doped GaN cladding layer 17.

[0009] According to the above method of forming the rough pattern, however, there is a problem of increase in resistance of the p-doped GaN cladding layer 17. That is, due to the dry etching of the p-doped GaN cladding layer 17, p-type dopants such as Mg in the p-doped GaN cladding layer 17 become less active, which does not allow a sufficient amount of charge carrier. In addition, it is highly likely that the active layer 15 may be damaged by the reactive ion or plasma during the dry etching of the p-doped GaN cladding layer 17. Consequently, the product yield turns out low.

[0010] In an alternative way to manufacture a light emitting device having a photonic crystal, the sapphire substrate is separated and then a rough pattern is formed on the upper surface of the n-doped GaN cladding layer using electron-beam lithography and dry etching to manufacture an LED having a vertical structure ("Watt-Class High-Output-Power 365 nm Ultraviolet Light Emitting Diodes" by Daisuke Morita et al., Japanese Journal of Applied Physics Vol. 43, No. 9A, 2004, pp. 5945-5950). However, with the sapphire substrate removed, it is very difficult to perform photo-etching on an upper surface of a thin-filmed GaN-based structure having a thickness of 10 .mu.m or less, even with a conductive substrate used as a mount. Accordingly, this leads to significant decrease in yield.

SUMMARY OF THE INVENTION

[0011] The present invention has been made to solve the foregoing problems of the prior art and it is therefore an object of the present invention to provide a method for providing a vertical group III-nitride light emitting device having improved light extraction efficiency, which requires easier manufacturing process, allowing a greater yield.

[0012] According to an aspect of the invention for realizing the object, there is provided a method for manufacturing a vertical group III-nitride light emitting device comprising steps of:

[0013] (i) forming an undoped GaN layer and an insulating layer sequentially on a basic substrate;

[0014] (ii) selectively etching the insulating layer to form an insulating pattern on the undoped GaN layer;

[0015] (iii) sequentially forming an n-doped Al.sub.xGa.sub.yIn.sub.(1-x-y)N layer, where 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, 0.ltoreq.x+y.ltoreq.1, an active layer and a p-doped Al.sub.mGa.sub.nIn.sub.(1-m-n)N layer, where 0.ltoreq.m.ltoreq.1, 0.ltoreq.n.ltoreq.1, 0.ltoreq.m+n.ltoreq.1, on the insulating pattern;

[0016] (iv) forming a conductive substrate on the p-doped Al.sub.mGa.sub.nIn.sub.(1-m-n)N layer;

[0017] (v) removing the basic substrate, the undoped GaN layer and the insulating pattern to expose a rough pattern on the n-doped Al.sub.xGa.sub.yIn.sub.(1-x-y)N layer; and

[0018] (vi) forming an n-electrode on a part of the exposed surface of the n-doped Al.sub.xGa.sub.yIn.sub.(1-x-y)N layer.

[0019] Preferably, the basic substrate is a sapphire substrate according to an embodiment of the present invention. The conductive substrate may comprise a silicon substrate or a metal substrate.

[0020] According to a preferred embodiment of the present invention, the insulating layer comprises a silicon oxide film or silicon nitride film.

[0021] According to an embodiment of the present invention, the step (v) includes: separating or removing the basic substrate using a laser lift-off process; removing the undoped GaN layer using dry etching or chemical mechanical polishing (CMP); and removing the insulating pattern using wet etching.

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