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  Method for manufacturing thin film transistor array panel for display deviceUSPTO Application #: 20070048910Title: Method for manufacturing thin film transistor array panel for display device Abstract: A gate wire including gate lines, gate electrodes, and gate pads and extending in a transverse direction is formed on a substrate. A gate insulating layer is formed thereafter, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. A conductive material is deposited and patterned to form a data wire inducing data lines intersecting the gate lines, source electrodes, drain electrodes, and data pads. A protective layer made of silicon nitride is deposited on the substrate, and an organic insulating layer made of a photosensitive organic insulating material is coated on the protective layer. The organic insulating layer is patterned to form an unevenness pattern on its surface and first contact holes exposing the protective layer opposite the drain electrodes. Subsequently, the surface of the organic insulating layer is treated using inactive gas such as Ar, and then the protective layer is patterned together with the gate insulating layer by photo etch using a photoresist pattern to form contact holes respectively exposing the drain electrodes, the gate pads, and the data pads. Next, indium-tin-oxide or indium-zinc-oxide is deposited and patterned to form transparent electrodes, subsidiary gate pads, and subsidiary data pads respectively connected to the drain electrodes, the gate pads and the data pads. Finally, a reflective conductive material is deposited and patterned to form reflecting films having respective apertures in the pixel area on the transparent electrodes. (end of abstract) Agent: Macpherson Kwok Chen & Heid LLP - San Jose, CA, US Inventors: Joo-Sun Yoon, Bong-Ju Kim, Seung-Gyu Tae, Hyun-Young Kim USPTO Applicaton #: 20070048910 - Class: 438149000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, On Insulating Substrate Or Layer (e.g., Tft, Etc.) The Patent Description & Claims data below is from USPTO Patent Application 20070048910. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] (a) Field of the Invention [0002] The present invention relates to a manufacturing method of a thin film transistor array panel for a display device. [0003] (b) Description of the Related Art [0004] At present, a liquid crystal display ("LCD") is one of the most widely used flat panel displays. An LCD, which includes two panels having electrodes and a liquid crystal layer interposed therebetween, controls the transmittance of light passing through the liquid crystal layer by realigning liquid crystal molecules in the liquid crystal layer with voltages applied to the electrodes. Among these LCDs, the most commonly used one provides at least one electrode on each panel and includes thin film transistors ("TFTs") switching the voltages applied to the electrodes. [0005] Generally, a panel with TFTs ("TFT array panel") includes, in addition to the TFTs, signal wires including gate lines transmitting scanning signals, data lines transmitting image signals, gate pads transmitting the scanning signals from external devices to the gate lines, and data pads transmitting the image signals from external devices to the data lines. The TFT array panel further includes, pixel electrodes electrically connected to the TFTs and located in respective pixel areas defined by the intersections of the gate lines and the data lines. [0006] In a reflective LCD or a transflective LCD, the pixel electrodes are made of a transparent conductive material such as indium tin oxide ("ITO") and overlap signal wires to ensure aperture ratio of pixels. Also, an insulating layer made of organic insulating material with low dielectric constant is formed between the signal wires and the pixel electrodes to minimize the interference of the signals transferred through them. [0007] Moreover, the pixel electrodes of the transflective LCD are made of using a reflective conductive material such as Al or Ag as well as ITO, and formed to have embossment for increasing the reflecting ratio of the pixel electrodes. The embossment of the reflecting film is formed by providing an organic insulating layer with unevenness under the pixel electrode. [0008] However, adhesiveness between the organic insulating layer and the ITO film is deteriorated when forming the ITO film on the insulating layer made of the organic insulating material. To solve the problem, the roughness of the surface of the organic insulating layer is increased by performing a plasma process before depositing the ITO film. [0009] However, contact resistance of a contact exposing the wire to be connected to the pixel electrode is increased since the organic material is re-deposited on the wire in the contact during the plasma process. SUMMARY OF THE INVENTION [0010] It is an object of the present invention to provide a TFT array panel and a manufacturing method thereof having good adhesiveness between an ITO film and an organic insulating film and minimizing contact resistance of a contact through which ITO is electrically connected to a wire. [0011] In order to solve the problems, the present invention forms a protective layer under an organic insulating layer and performing surface-treatment of the organic insulating layer by a plasma process before deposition of an ITO film under the condition that the protective layer is remained on a wire. [0012] In detail, in a method of manufacturing a thin film transistor array panel according to the present invention a gate wire including a gate line and a gate electrode connected to the gate line is formed, a gate insulating layer is deposited, a semiconductor layer is formed, and a data wire including a data line intersecting the gate lines to define a pixel area, a source electrode connected to the data line and placed close to the gate electrode, and a drain electrode placed opposite the source electrode with respect to the gate electrodes is formed. Subsequently, a protective layer is deposited, then an organic insulating layer is formed by spin-coating an organic insulating material on the protective layer, the organic insulating layer is patterned to form a first contact hole exposing the protective layer opposite the drain electrode, and a surface of the organic insulating layer is treated by plasma process using inactive gas. Also, the protective layer is patterned to form a second contact hole exposing the drain electrode and located inside the first contact hole and a pixel electrode electrically connected to the drain electrode through the first and the second contact holes is formed. [0013] The pixel electrode may include a transparent conductive electrode or a reflective conductive film. The surface of the organic insulating layer preferably has an unevenness pattern when the pixel electrode has the reflective film. The reflective film has an aperture in the pixel area. [0014] The semiconductor layer may include amorphous silicon or poly silicon. The protective layer may include SiNx or SiOx. Preferably, the second contact hole may be formed by a photo etch using a photoresist pattern after forming the first contact hole. [0015] It is preferable that the gate wire further includes a gate pad connected to one end of the gate line, the data wire further includes a data pad connected to one end of the data line, and the protective layer or the gate insulating layer has a third contact hole exposing the gate pad or the data pad. The thin film transistor array panel preferably further includes a subsidiary pad electrically connected to the gate pad or the data pad through the third contact hole and including substantially the same layer as the pixel electrode. [0016] Both the data wire and the semiconductor layer may be formed by a photo etch step using a photoresist pattern with position-dependent thickness. BRIEF DESCRIPTION OF THE DRAWINGS [0017] FIG. 1 is a layout view of a TFT array panel for a transflective type LCD according to a first embodiment of the present invention; [0018] FIG. 2 is a sectional view of FIG. 2 taken along the line II-II'; [0019] FIGS. 3A, 4A, 5A, 6A, 8A and 9A are layout views of a TFT array panel for a transflective type LCD in the intermediate steps of a manufacturing method thereof according to an embodiment of the present invention; [0020] FIG. 3B is a sectional view of the TFT array panel shown in FIG. 3A taken along the line IIIB-IIIB'; [0021] FIG. 4B is a sectional view of the TFT array panel shown in FIG. 4A taken along the line IV-IV' and illustrates the step following the step shown in FIG. 3B; Continue reading... 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