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  Method for manufacturing semiconductor deviceUSPTO Application #: 20070059853Title: Method for manufacturing semiconductor device Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced. (end of abstract) Agent: Miles & Stockbridge PC - Mclean, VA, US Inventors: Atsushi KUROKAWA, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura USPTO Applicaton #: 20070059853 - Class: 438022000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Device Or Circuit Emissive Of Nonelectrical Signal The Patent Description & Claims data below is from USPTO Patent Application 20070059853. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique which can be effectively used for the manufacturing of high frequency power amplifier which is mainly comprised of hetero junction bipolar transistors (HBT) which constitute ultrahigh-speed IC elements. [0002] As a semiconductor device which exhibits high speed performance and low power consumption performance, a hetero junction bipolar transistor (hereinafter also referred to as HBT) has been known. This hetero junction bipolar transistor is used in a form that the transistor is incorporated into a high frequency power amplifier (RF power amplifying module) of a mobile communication terminal such as a portable cellular phone. [0003] The HBT has a structure in which a sub-collector layer and a collector layer are sequentially laminated onto one surface (main surface) of a semiconductor substrate, a base layer is partially formed over the collector layer, and an emitter layer which is formed of a semiconductor having a wide band gap is partially formed over the base layer. [0004] In a power amplifying device for transmission in a communication system, the HBT has now been used as a transistor. Such a semiconductor device is described in Japanese Laid-open Patent 210723/2001. [0005] In Japanese Laid-open Patent 210723/2001, a technique for manufacturing a semiconductor device having a bias circuit which suppresses a change of an idle current attributed to a temperature change of a power transistor Tr1 is disclosed. Such a semiconductor device is manufactured using a GaAs substrate as a base and, for compensating for a temperature shift of the idle current, a plurality of Schottky diodes are provided to a base inputting part. The bias circuit is constituted of two transistors (Tr2, Tr3) which are connected to the power transistor Tr1, two Schottky diodes (D1, D2) and three resisters (R1 to R3). [0006] That is, a base terminal of the power transistor Tr1 is connected to a collector terminal of the transistor Tr2 through a resistor R3 in an emitter follower method, and a base terminal of the transistor Tr2 is grounded through the transistor Tr3 which short-circuits a base and a collector of the Schottky diodes D1, D2 thus suppressing the change of the idle current C of the transistor Tr1 which is generated when the temperature changes. [0007] Further, with respect to this semiconductor device, base electrodes and the Schottky electrodes of the HBT are simultaneously formed at the time of manufacturing the semiconductor device. [0008] On the other hand, in the manufacturing of the HBT, for preventing an excessive etching of the sub-collector layer, there has been known a technique which provides an InGaP layer between the sub-collector layer and the collector layer. This technique is described in IEEE Electron Device Lett., vol. 18, p355, 1997. [0009] Further, in IEEE Electron Device Lett., vol. 18, p559, 1997, there is disclosed a technique which enhances the isolation performance by arranging an undoped InGaP layer having a resistance higher than a resistance of an undoped GaAs layer below a collector layer. SUMMARY OF THE INVENTION [0010] As a transistor which constitutes a high frequency power amplifier (RF power module) for a mobile communication unit, a hetero junction bipolar transistor (HBT) which constitutes a ultra high-speed IC element has been used. Further, to compensate for a temperature shifting of an idle current in the transistor, a bias circuit which provides a plurality of Schottky diodes to a base inputting part is incorporated. Resistance elements are also incorporated in this bias circuit. [0011] The reduction of manufacturing cost has been requested with respect to the HBT in the same manner as other transistors and modules. With respect to the power transistor into which the bias circuit is incorporated, as described in the above-mentioned literature, there has been proposed the method which simultaneously forms the Schottky electrodes and the base electrodes using a same material. [0012] To explain manufacturing steps thereof, as shown in FIG. 23(a), a semiconductor layer (n.sup.+ type GaAs layer) below an emitter electrode 56 is etched using the emitter electrode 56 as a mask until the etching reaches a surface of a semiconductor layer (n type InGaP layer) which constitutes a wide gap emitter layer 54 below the semiconductor layer (n.sup.+ type GaAs layer) thus forming a mesa-shaped emitter layer 55. [0013] Thereafter, an etching mask not shown in the drawing is formed and, as shown in FIG. 23(a), using this etching mask as a mask, a semiconductor layer which constitutes the wide gap emitter layer 54 which is exposed in a periphery of the emitter layer 55, a semiconductor layer (p-type GaAs layer) which constitutes a base layer 53 below the semiconductor layer, and a semiconductor layer (n.sup.+ type GaAs layer) 52a which constitutes a collector layer below the base layer 53 are sequentially etched, wherein the semiconductor layer 52a is etched to an intermediate depth thereof, thus forming the base layer having a mesa shape (mesa-shaped base layer) 53. [0014] Subsequently, a base electrode 57 and a Schottky electrode 58 are simultaneously formed, wherein the base electrode 57 is formed over the wide gap emitter layer 54 in the periphery of the emitter layer 55 and the Schottky electrode 58 is formed over the semiconductor layer (n.sup.+ type GaAs layer) 52a which constitutes a collector layer in a Schottky diode forming region which is disposed away from a region where the HBT is formed. The base electrode 57 is subjected to an alloying treatment (heating treatment). [0015] As a result, the wide gap emitter layer 54 below the base electrode 57 is alloyed so that a base electrode 57 and the base layer 53 are electrically connected to each other. [0016] Further, in the manufacturing of the HBT, as shown in FIG. 23(a), a substrate (wafer) which is eventually produced by sequentially forming respective semiconductor layers consisting of a sub collector layer 51, the collector layer 52, the mesa-shaped base layer 53, the wide gap emitter layer 54 and the emitter 55 over one surface (main surface) of a semi-insulation GaAs substrate 50 is used. [0017] However, in the method which forms the base electrode over the semiconductor layer which constitutes the wide gap emitter layer 54, it is necessary to form holes for forming the base electrode in the etching mask. Accordingly, in view of the mask alignment tolerance for forming this hole, it is necessary to ensure the mask alignment tolerance length between an outer periphery of the base electrode 57 and an outer periphery of a mesa-shaped base layer 53 in FIG. 23(b). As a result, a junction area between the base layer 53 and the collector layer 52 is increased. The increase of the area between the base and the collector deteriorates the high frequency characteristics (for example, maximum oscillation frequency f max). [0018] Then, as shown in FIG. 24, when the mask alignment tolerance length is shortened, the outer periphery of the base electrode 57 extends beyond the periphery of the mesa-shaped base layer 53 and is brought into contact with the collector layer 52 (contact portion 70) thus giving rise to a short-circuit defect. This leads to the lowering of a yield factor and brings about a drawback that a manufacturing cost is pushed up. [0019] To prevent the outer periphery of the base electrode 57 from extending beyond the mesa-shaped base layer 53 and coming into contact with the semiconductor layer (n.sup.+ type GaAs layer) 52a which constitutes the collector layer, it is necessary to ensure a minimum mask alignment tolerance length "a". FIG. 25 is a schematic view for showing the size relationship among respective portions in the manufacturing of the HBT while ensuring the mask alignment tolerance length "a". [0020] A base-collector junction length L2 is a length which is obtained by adding 2.times. mask alignment tolerance length "a" to a distance (distance between outer peripheries) "b" between one outer periphery of the base electrode 57 and another outer periphery which is disposed opposite to one outer periphery of the base electrode 57 and hence, the high frequency power amplifier becomes large-sized. The distance between outer peripheries ("b") is a sum of a width "d" of the base electrode 57, a length "c" of the emitter electrode 56 and a distance "e" from a periphery of the emitter electrode 56 to an inner periphery of the base electrode 57. [0021] The inventors of the present invention have studied the above-mentioned distances and widths from a viewpoint of miniaturization of the HBT element and have obtained following sizes of respective portions as a result of the study. That is, the lengths and the widths are set such that c=4 .mu.m, d=1 .mu.m, e=1 .mu.m and b=8 .mu.m. Further, by setting the mask alignment tolerance length "a" as a=0.8 .mu.m, the base-collector junction length L2 becomes 9.6 .mu.m. [0022] On the other hand, to ensure the insulation separation (isolation) between the HBT and the other element arranged close to the HBT, there has been known a structure which provides a separation groove between the elements by etching. In performing this etching, when the etching is insufficient, the separation groove is not formed thus giving rise to a short-circuit defect, while when the etching is excessive, a large stepped portion is formed and hence, a line which is arranged traversing the stepped portion is disconnected due to the large stepped portion. Continue reading... Full patent description for Method for manufacturing semiconductor device Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method for manufacturing semiconductor device patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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