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Method for manufacturing dual damascene structure with a trench formed firstRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects)Method for manufacturing dual damascene structure with a trench formed first description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060194426, Method for manufacturing dual damascene structure with a trench formed first. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] This application is a division of U.S. patent application Ser. No. 10/919,328, filed Aug. 17, 2004. [0002] The present invention relates to a method of manufacturing a dual damascene structure, and more particularly, to a method of manufacturing a dual damascene structure with a trench formed first. BACKGROUND OF THE INVENTION [0003] The manufacture of integrated circuits (ICs) usually adopts multilevel interconnects to build up 3-D interconnection structures in highly dense devices, as IC device performance extends to higher levels. In devices, the metal lines of the first layer are generally electrically coupled to the drains/sources of devices through vias, and the interconnects between the devices are coupled by the metal lines of other layers. On the other hand, the multilevel interconnects between the metal lines are separated by inter-metal dielectric (IMD) layers, while the respective metal layers are connected by via plugs. The dual damascene process is currently developed for forming via plugs and metal interconnects at the same time. [0004] As to the metals, copper is gradually being substituted for aluminum, because copper comprises the properties of a high melting point and a low resistance (about 1.7 .mu..OMEGA.-cm), and is more capable of preventing electro-migration. However, copper itself is inclined to oxidize and tends to react with other materials at low temperatures. Further, no effective dry etching process exists for copper. Nevertheless, these issues are overcome by improved diffusion barrier materials and progressive processes, such as damascene process, and chemical mechanical polishing (CMP). [0005] FIGS. 1A-1E illustrate a conventional method of manufacturing dual damascene. Referring to FIG. 1A, a semiconductor substrate 101 with a plurality of semiconductor devices (not shown) is provided. A metal layer 103, a first etching stop layer 107, an inter-metal dielectric layer 109, and a second etching stop layer 111 are subsequently formed thereon. A photoresist layer 113 is then coated and patterned to define the position of a via. [0006] The via 116 is formed by etching the second etching stop layer 111, the inter-metal dielectric layer 109, and the first etching stop layer 107, as illustrated in FIG. 1B. In this step, the metal layer 103 has been exposed to air. As a result, a baking step should now be performed to prevent the metal layer 103 oxidation. After that, a sacrificial layer 115 is filled therein. [0007] In turn, the sacrificial layer 115 is etched back, and a photoresist layer 117 is next coated thereon, as shown in FIG. 1C. Referring to FIG. 1D and FIG. 1E, the photoresist layer 117 is patterned and etched to form a trench 118. After the photoresist layer 117 and the sacrificial layer 115 are removed, a metal layer 119 is then filled therein. [0008] According to the aforementioned description, the conventional method for manufacturing dual damascene is to form a trench following a via. This method, however, conceals some problems. As mentioned above, the metal layer 103 has been exposed to air before the sacrificial layer 115 is filled therein. Using copper as the metal layer dramatically affects the quality of the devices, since copper is inclined to oxidize. Therefore the queue time (Q-time) should be controlled precisely. [0009] Moreover, micro trenches 203 and fences 201 issues commonly occur in the conventional process, as shown in FIG. 2, that affect the subsequent processes. For example, fences cause poor coverage capability of barrier layers and electrochemical plating (ECP) deposition. Fences, for instance, further result in unsteady electrical properties, as well as poor reliability of devices. [0010] In addition, the dielectric layer 109 is generally constituted by porous low-k materials, through which residual NH-group components in the substrate readily pass to neutralize with the photoresist layer, and consequently react to be photoresist scum. Therefore the photoresist is not developed and patterned well, which also leads to a decrease in the production yield. SUMMARY OF THE INVENTION [0011] One of the objectives of the present invention is to provide a method for manufacturing a dual damascene structure with a trench formed first, in order to reduce Q-time when copper is exposed to the air and also to simplify the process by omitting a post-baking step following etching a via. [0012] Another objective of the present invention is to improve the surface quality of the photoresist layer for etching a via by planarizing the sacrificial layer. The photolithography process thus has a wider control window. [0013] Yet another objective of the present invention is to provide a method for manufacturing a dual damascene structure with a trench formed first. No photoresist scum issue is caused by neutralization of the photoresist with NH-- group components due to the greater open area of the trench. The photoresist is therefore patterned and transferred more clearly and more precisely. [0014] Yet another objective of the present invention is to provide a method for reducing micro trenches and fences by means of a sacrificial layer with substantially the same etching rate selectivity as an inter-metal dielectric layer; both of which and the photoresist are consequently easily stripped by a wet or dry cleaning process or by a wet or dry etching process. [0015] According to the aforementioned objectives of the present invention, a method for manufacturing a dual damascene structure with a trench formed first is provided. The method of manufacture has the following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, a second etching stop layer, and a first patterned photoresist layer are subsequently formed thereon. The first patterned photoresist layer is used as a mask, and a trench is then formed by etching through the second etching stop layer and stopping in the dielectric layer at a predetermined depth. The trench is filled with a sacrificial layer thereafter and is next planarized. Then a second patterned photoresist layer is formed thereon as a mask for etching a via. The second patterned photoresist layer and the sacrificial layer are then both removed. The first etching stop layer is next etched through to expose the first metal layer. A second metal layer is subsequently filled therein and is also planarized. [0016] The first metal layer and the second metal layer discussed above comprise copper, while the dielectric layer comprises fluorinated silicate glass (FSG), silicon dioxide, black diamond (BD), SiLK, CORAL, methyl silsesquioxane (MSQ), or hydrogen silsesquioxane (HSQ), of which the dielectric constant is preferably from about 1.0 to about 4.0. [0017] The predetermined depth of the trench discussed above is preferably less than the thickness of the dielectric layer, yet the sacrificial layer is 0.5-1.5 times the thickness of the dielectric layer. The etching rate ratio of the sacrificial layer to the dielectric layer, moreover, is around 0.7:1 to 1.3:1. On the other hand, the second patterned photoresist layer and the dielectric layer are separated by the sacrificial layer and the second etching stop layer to prevent the photoresist layer from contacting NH-- group components. Additionally, the photoresist layer is positioned on the sacrificial layer that has been planarized, so the photoresist layer is more capable of being patterned and transferred. [0018] The method for manufacturing a dual damascene structure with a trench formed first in accordance with the present invention not only reduces the Q-time when copper is exposed to the air, but also eliminates one step of baking, by which the process is effectively simplified. Furthermore, the problems of micro trenches and fences, as well as the issue of neutralization of the photoresist layer with the NH-- group components are successfully solved; as a result, the control window of the photolithography process is increased. BRIEF DESCRIPTION OF THE DRAWINGS [0019] The foregoing aspects and many of the attendant advantages of this invention will become more apparent by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: [0020] FIGS. 1A-1E illustrate cross-sectional views of various stages of a method for manufacturing dual damascene in the prior art; Continue reading about Method for manufacturing dual damascene structure with a trench formed first... Full patent description for Method for manufacturing dual damascene structure with a trench formed first Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method for manufacturing dual damascene structure with a trench formed first patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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