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06/07/07 - USPTO Class 228 |  82 views | #20070125833 | Prev - Next | About this Page  228 rss/xml feed  monitor keywords

Method for improved high current component interconnections

USPTO Application #: 20070125833
Title: Method for improved high current component interconnections
Abstract: A printed circuit board having at least one conductive region covered in solder paste has preformed solder elements placed on the solder paste in the conductive region. A component package is placed onto the printed circuit board over the conductive region and the solder is reflowed, forming a wide solder interconnection between the component and the conductive region of the printed circuit board. (end of abstract)



Agent: Intel/blakely - Los Angeles, CA, US
Inventors: Dudi I. Amir, Damion T. Searls
USPTO Applicaton #: 20070125833 - Class: 228101000 (USPTO)

Related Patent Categories: Metal Fusion Bonding, Process

Method for improved high current component interconnections description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20070125833, Method for improved high current component interconnections.

Brief Patent Description - Full Patent Description - Patent Application Claims
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[0001] This application is a divisional of prior application Ser. No. 10/427,681, filed Apr. 30, 2003.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to the field of electronic printed circuit boards, and more specifically to forming solder interconnections on the printed circuit board.

[0004] 2. Discussion of Related Art

[0005] Demands on power delivery have increased as part of the effort to achieve higher performance in logic silicon products. Higher currents, better current transient response and bypass capacitance are frequently the key parameters sought in successful power delivery design. One potential power delivery bottleneck is in the printed circuit board-component interface. For example, a power MOSFET-board interface can introduce a substantial amount series resistance and thereby limit the effectiveness of the power delivery system. Currently, many standard off-the-shelf ball grid array (BGA) MOSFET components use similar interconnect structures for both the power and signal connection even though the electrical and thermal requirements for power and signaling can be different.

[0006] FIGS. 1A, 1B, and 1C illustrate an exemplary means of the current art for forming an interconnection between a component in a standard BGA package 102 and a printed circuit board 100. FIG. 1A illustrates a top view of a printed circuit board 100 with component 102 positioned above it. The printed circuit board conductive planes 106 extend underneath the BGA component package 102. The conductive planes may be either power or ground planes. These planes are covered by an array of individual solder paste pads 108. The printed circuit board also contains signal traces 105 that are each connected to a conductive pad covered with solder paste 108. Individual solder balls 120 from the BGA component package 102 form the connection between the pads and the component for both the signal interconnections and the conductive plane interconnections.

[0007] FIG. 1B illustrates a side view of component 102 positioned over printed circuit board 100. Component solder balls 120 are positioned over solder paste pads 108, connecting component solder balls 120 to signal pads 104 and conductive plane 106. Solder mask 101 protects areas of the printed circuit board that are not to be covered by solder.

[0008] FIG. 1C illustrates the component 102 and printed circuit board 100 of FIG. 1B after the component solder balls 120 and solder paste 108 have been reflowed to form an electrical interconnection 122. Although the component standoff 126 created by this method may be adequate, the electrical interconnection between the component 102 and the printed circuit board is quite narrow in the conductive plane region 106.

[0009] The relatively low volume solder ball of the BGA limits the size of the component--power plane interface. The smaller interconnects 122 formed using the prior art method limit current to the component. These smaller interconnects are highly resistive, and can limit the effectiveness of the power delivery system. In addition, the resulting high current density can result in excessive parasitic inductance. It is advantageous to remove this bottleneck by widening the power interface. A wider power interface has several advantages, including reduced resistance and increased heat transfer between the package and the printed circuit board. Though a wider power interface is desired, it is also advantageous to avoid altering the design of a commodity product like a MOSFET.

[0010] As illustrated in FIGS. 2A and 2B, a wider conductive interconnection may be formed on the printed circuit board by replacing an array of solder paste pads over a conductive region with a larger region of solder paste 109. This may not provide for an optimal solder interconnection, however. Solder paste 108 covers signal pads 104, forming an interconnection 122 between the signal pads and the component solder balls after solder reflow. Solder paste region 109 covers conductive plane 106, forming an interconnection 123 between the conductive plane and the component solder balls after solder reflow. As illustrated in FIG. 2B, the volume of solder provided by solder paste region 109 and solder balls 120 may not be sufficient to entirely fill the solder interconnection area 123 after solder reflow. Solder voids 124 and solder separation will result from insufficient solder volume. Furthermore, the resulting component standoff 126 will be less than the desired standoff when an inadequate amount of solder is used in forming interconnections.

[0011] In some cases, additional solder volume can be provided by the component, either by adding additional solder balls to the component, or by using larger solder balls on the component. However, this requires a change in product design by the component vendor to accommodate the additional solder on the component package.

[0012] FIGS. 3A and 3B illustrate an exemplary means of the current art for providing a wider power interface between the component and the printed circuit board. FIG. 3A illustrates a bottom view of a standard component package 102 containing no solder. Conductive pads 121 and signal pad 122 are located on the bottom of component package 102.

[0013] FIG. 3B illustrates the interconnect formed between package 102 and printed circuit board 100 after the conductive pads of the component are placed onto a layer of solder paste and the solder paste is reflowed. After reflow, solder interconnections 123 are formed between conductive pads 121 and conductive planes 106, and between conductive signal pad 122 and signal pad 104. The component package 102 contains no solder on either conductive pads 121 or signal pad 122, so the manufacturer must rely on solder paste alone to make up the entire solder volume of the solder interconnect between the component and the printed circuit board. Because of limitations on the amount of solder paste that can practically be applied to the printed circuit board, the solder paste alone provides insufficient solder volume to entirely fill the solder interconnections 123. Solder separation may occur, or solder voids 124 may be formed with the solder interconnections 123. Furthermore, the component standoff 126 formed by this method is less than the ideal component standoff. To avoid these problems, additional solder volume must be added to the solder interconnection.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIGS. 1A, 1B, and 1C illustrate a prior art method for forming an interconnection between a standard BGA component and a printed circuit board.

[0015] FIGS. 2A and 2B illustrate problems associated with forming an interconnection between a standard BGA component and a printed circuit board having a widened power interface.

[0016] FIGS. 3A and 3B illustrate a prior art method for widening the power interconnection between a component and a printed circuit board, wherein the component package contains no solder.

[0017] FIG. 4A illustrates a top view of an exemplary printed circuit board and solder paste stencil prior to solder paste application according to one embodiment of the present invention.

[0018] FIG. 4B illustrates a cross-section view of an exemplary printed circuit board and solder paste stencil prior to solder paste application according to one embodiment of the present invention.

[0019] FIG. 5A illustrates a top view of an exemplary printed circuit board after solder paste application according to one embodiment of the present invention.

[0020] FIG. 5B illustrates a cross-section view of an exemplary printed circuit board after solder paste application according to one embodiment of the present invention.

[0021] FIG. 6A illustrates a top view of an exemplary printed circuit board and bonus solder ball stencil according to one embodiment of the present invention.

[0022] FIG. 6B illustrates a cross-section view of an exemplary bonus solder ball stencil according to one embodiment of the present invention.

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