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Method for forming raised structures by controlled selective epitaxial growth of facet using spacerRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Junction Field Effect Transistor (unipolar Transistor), Junction Field Effect Transistor In Integrated Circuit, With Devices Vertically Spaced In Different Layers Of Semiconductor Material (e.g., "3-dimensional" Integrated Circuit)Method for forming raised structures by controlled selective epitaxial growth of facet using spacer description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060289902, Method for forming raised structures by controlled selective epitaxial growth of facet using spacer. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] The present application is a division of U.S. patent application Ser. No. 10/379,494, filed on Mar. 4, 2003, presently pending, which is a division of U.S. patent application Ser. No. 10/046,497, filed on Oct. 26, 2001, presently pending, which is a division of U.S. patent application Ser. No. 09/816,962, filed Mar. 23, 2001, presently pending. FIELD OF THE INVENTION [0002] The present invention relates to the field of semiconductor device fabrication, and more particularly to vertical transistors and other raised structures of a semiconductor device that are formed by controlled selective epitaxial growth. BACKGROUND OF THE INVENTION [0003] The storage capacity of a memory chip is dependent on the number of memory cells in the chip. High density dynamic random access memory (DRAMs) cells are comprised of two main components, a field-effect transistor (FET) and a storage capacitor. In DRAM fabrication, there is a continuing need to provide higher density memories in order to further increase data storage capacity. [0004] Increasing circuit density in DRAM fabrication requires a reduction in the size of the FETs and storage capacitors of memory cells. As a solution to this problem, trench capacitors, vertically stacked capacitors, elevated source and drain structures, and other improved structures have been developed which require less surface area. However, photolithographic processing limits the minimal size of the feature and the resulting device that can be formed. Thus, the density of storage cells of a memory array has been limited by the resolution capability of the available photolithographic equipment. [0005] Therefore, there is a need for a semiconductor fabrication technique to provide high density memory structures that can be fabricated without the limitations of photolithographic processing steps. SUMMARY OF THE INVENTION [0006] The present invention relates to elevated structures such as transistors and raised source/drain regions formed on a semiconductor substrate by controlled growth of epitaxial layers, and methods for forming such structures. [0007] The invention utilizes selective epitaxial growth (SEG) to form vertically oriented structures on semiconductor substrates. Crystal growth by SEG along a select facet to form a vertically oriented structure cannot be controlled by varying the growth conditions due to the existence of facets on the crystal having different orientations i.e., (100), (110), (111). However, such control is needed to achieve vertically oriented epitaxial growth and eliminate lateral or horizontal growth that can short circuit closely positioned adjacent devices. The present method employs insulative spacers formed over the sidewalls of the epitaxial layers to eliminate unwanted lateral growth and control the growth of the epitaxial film. [0008] In one aspect, the present invention provides a method for forming a vertical structure on a semiconductive substrate by selective epitaxial growth. An exemplary semiconductive substrate comprises monocrystalline silicon having a (100) orientation. [0009] In one embodiment of the method of the invention, a vertical structure can be formed on a semiconductive substrate. The method involves selectively growing a first epitaxial layer of monocrystalline silicon on the surface of the substrate. Prior to the SEG step, it is desirable to remove oxide from the area on the substrate where the structure is to be formed, for example, by a dry oxide etch. The semiconductive substrate is exposed to a silicon-comprising gas in an epitaxial (epi) growth chamber for a time and under conditions effective to form an epitaxial layer of monocrystalline silicon having a faceted surface. The epitaxial layer comprises a single silicon crystal having vertically oriented sidewalls and a top horizontal surface, preferably defining a facet having a (100) plane orientation. [0010] Upon forming the initial epitaxial layer on the surface of the substrate, a thin film of insulative material is formed over the epitaxial layer. Preferably, the insulation layer is formed by rapid thermal annealing, i.e., rapid thermal oxidation (RTO) to form an oxide film, or by rapid thermal nitridation (RTN) to form a nitride film. A portion of the insulative layer is then removed, preferably by reactive ion etching (RIE), to expose only the top (horizontal) surface of the epitaxial layer, with the insulative material remaining along the sidewalls as a spacer. A second epitaxial layer of monocrystalline silicon is grown by SEG on the exposed horizontal surface of the initial epitaxial layer. A thin insulative film is then formed over the second epitaxial layer. Further epitaxial layers can be similarly added to increase the height of the structure as desired, by repeating the foregoing steps. [0011] The resultant vertically-oriented structure comprises multiple epitaxial layers having insulated sidewalls, with the uppermost layer having an insulated top surface. The structure can function, for example, as a vertical gate or word line of a DRAM cell, in which case it is preferred that the semiconductive substrate underlying the structure is lightly doped with a conductivity enhancing material. Source/drain regions can be formed adjacent to the structure by conventional methods, or as an elevated structure by the method of the invention, as described below. [0012] In another embodiment of the method of the invention, a vertical structure of a desired height can be formed adjacent to an existing transistor gate or word line on a substrate. The gate or word line can be formed by the method of the invention, or by conventional methods known in the art. In forming vertical source/drain structures, the structures comprise a sufficient amount of a conductivity enhancing dopant to effectively provide the source and drain regions. The doping step can be performed during one or more SEG steps by flowing a silicon-comprising gas combined with a conductivity enhancing dopant onto the substrate, or after the structures have been formed by ion implantation. [0013] According to another embodiment of the method of the invention, a plurality of elevated transistors can be formed on a substrate so as to define an array of transistors. The transistors can be isolated by areas of insulative material, such as shallow trench isolation regions comprising an oxide. [0014] In yet another embodiment of the method, an elevated transistor can be formed on a semiconductive substrate, the transistor comprising a buried drain, a vertical gate, and an overlying source region. The buried drain can be formed in a semiconductive substrate by conventional ion implantation processing. An elevated gate can be formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the substrate overlying the drain, depositing an insulative layer over the epitaxial layer, and selectively removing the horizontal surface of the insulative layer to expose only the top surface of the epitaxial layer. Additional epitaxial layers can be added by repeating the SEG step, and depositing the insulative layer, and selectively removing the insulative layer to maintain insulative material along the sidewalls as spacers to limit the growth of the epitaxial layer in a vertical orientation, resulting in a pillar-like gate structure having a desired height. A source region can then be formed by SEG above the uppermost epitaxial layer of the gate. To do so, a conductivity enhancing dopant can be added while the epitaxial layer is being deposited, or after the formed epitaxial layer is formed, for example, by ion implantation. [0015] In another aspect, the invention provides raised structures comprising multiple layers of monocrystalline silicon formed by controlled selective epitaxial growth. An exemplary structure is a transistor comprising source/drain diffusion regions adjacent to a transistor gate, one or more of the foregoing components of the transistor comprising multiple epitaxial layers having insulated sidewalls and a top surface. [0016] In one embodiment of a transistor, the transistor gate comprises at least two overlying layers of epitaxially grown silicon, each epitaxial layer comprising a single silicon crystal having a top or upper surface defining a facet, preferably having a (100) plane orientation, and vertically-oriented and insulated sidewalls. The uppermost epitaxial layer of the gate also has an insulated top surface, such that the gate is covered by a layer of insulative material. The gate is a vertical structure that is oriented in a vertical plane from the substrate surface. The source/drain comprises diffusion regions adjacent to the transistor gate within the semiconductive region, and can be formed according to known methods in the art. [0017] In another embodiment of a transistor according to the invention, the source/drain regions are elevated structures that extend in a vertical plane from the substrate. The transistor gate comprises an existing vertical structure between the source/drain regions, which can be formed according to known methods in the art or in accordance with the invention. The source/drain structures comprise at least two overlying layers of epitaxially grown silicon, each epitaxial layer comprising a single silicon crystal having a top surface and vertically oriented insulated sidewalls. Preferably, the top surface of the epitaxial layers defines a facet having a (100) plane orientation. The top surface of the uppermost epitaxial layer is also insulated. The source/drain regions also comprise a conductivity enhancing dopant that is added as the epitaxial layers are deposited, or afterwards to the formed structure by ion implantation prior to depositing the insulative layer onto the uppermost epitaxial layer of the structure. [0018] In yet another embodiment of a transistor according to the invention, both the transistor gate and the adjacent source/drain regions are vertical structures comprising multiple epitaxial layers having insulated sidewalls and an insulated top surface on the uppermost epitaxial layer. [0019] A further embodiment of a transistor according to the invention comprises a drain buried within a semiconductive substrate, a vertical gate overlying the buried drain, and a source region overlying the gate. The vertical gate comprises at least two overlying layers of epitaxially grown silicon having sidewalls covered by an insulative material, with the uppermost epitaxial layer having a layer of insulative material over its top surface. The drain can comprise a doped area within the substrate underlying the gate. The source region comprises at least one layer of epitaxially grown silicon overlying the uppermost layer of the gate. The epitaxial layer of the source region has insulated sidewalls and on top surface, and is doped with a conductivity enhancing dopant. [0020] The invention provides useful and improved vertically oriented structures such as transistor gates and elevated source/drain regions that extend outwardly from a substrate. Such structures are particularly suited for use in a DRAM cell or other semiconductor structure. The vertical nature of the structures allows a larger number of transistors or other semiconductor structures per surface area compared to conventional devices. Continue reading about Method for forming raised structures by controlled selective epitaxial growth of facet using spacer... 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