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  Method for forming a semiconductor device having a strained channel and a heterojunction source/drainUSPTO Application #: 20060068553Title: Method for forming a semiconductor device having a strained channel and a heterojunction source/drain Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel. (end of abstract) Agent: Freescale Semiconductor, Inc. Law Department - Austin, TX, US Inventors: Voon-Yew Thean, Mariam G. Sadaka, Ted R. White, Alexander L. Barr, Venkat R. Kolagunta, Bich-Yen Nguyen, Victor H. Vartanian, Da Zhang USPTO Applicaton #: 20060068553 - Class: 438285000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Utilizing Compound Semiconductor The Patent Description & Claims data below is from USPTO Patent Application 20060068553. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application is related to our copending U.S. Patent Application, (Attorney Docket No. SC-13377TP) entitled "Double Gate Device Having A Heterojunction Source/Drain and a Strained Channel", filed simultaneously herewith and assigned to the assignee hereof. FIELD OF THE INVENTION [0002] This invention relates generally to semiconductor, and more specifically, to making semiconductor devices having very small dimensions. BACKGROUND OF THE INVENTION [0003] Semiconductor devices, such as transistor structures, continue to be scaled to smaller dimensions as process lithography improves. However, different challenges have been encountered in the scaling of transistor structures much below 100 nm. Additionally, when transistor dimensions on the order of 100 nm and smaller are used, implants cannot be adequately controlled with conventional semiconductor fabrication equipment. Channel dopant fluctuations adversely affect device uniformity within circuits. To control a conventional bulk transistor's threshold voltage which is the voltage at which the transistor becomes conductive, dopants in the channel are used. However, channel doping is not an efficient method for ultra-thin devices due to the large amount of channel impurities that are required. Therefore, highly doped ultra-thin devices are even more susceptible to threshold voltage fluctuations. Additionally, high channel doping concentrations degrade both electron and hole mobility and promote source/gate and drain/gate junction leakage. [0004] A technique to improve bulk transistor performance is to provide a bulk transistor having a strained channel. Such devices are structured to place a strain on the transistor's channel. An appropriately strained channel results in electron and hole mobility enhancement that increases the conduction current which provides a higher device drive performance. [0005] One method to form a transistor having a strained channel is to recess silicon material in those areas where the source and drain are to be formed and re-grow a stressor material in the recessed areas. However, when thin-body devices are being implemented, the depth available for the stressor material is insufficient to adequately strain the channel. Another issue with this technique is that the silicon material is recessed with an etch process. Stopping the etch process at a desired depth is a challenge and subject to variation. Additionally, re-growth of the stressor material on the remaining ultra-thin silicon is problematic. Also, the ultra-thin silicon can agglomerate at temperatures required for growing the stressor material. Additionally, this method does not apply to the known FINFET structures or any thin-body transistor devices. [0006] Another known method to induce stress into a channel is the use of a substrate as a stressor material. A shortcoming with this approach is that when the stressor material is SiGe, the SiGe causes degradation of the gate dielectric due to increased interface states when the Ge diffuses to the dielectric semiconductor interface. The material SiGe has a narrow bandgap. Therefore, another issue with this approach is that the presence of SiGe in the transistor's channel increases the transistor's off-state current leakage. Additionally, this method does not apply to the known FINFET structures or any vertical thin body double gate transistor. [0007] Yet another known method of stressing a transistor channel is the use of overlying stress inducing layers over the active regions of the transistor. However, the stressor material is located far enough from the channel so that the influence of the stressor material on the channel is diminished. BRIEF DESCRIPTION OF THE DRAWINGS [0008] The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements. [0009] FIGS. 1-5 illustrate in cross-sectional form a method of forming an ultra-thin body transistor in accordance with one form of the present invention; [0010] FIGS. 6-9 illustrate in cross-sectional form a method of forming an ultra-thin body transistor in accordance with another form of the present invention; [0011] FIGS. 10-15 illustrate in cross-sectional form an ultra-thin double gate device in accordance with one form of the present invention; [0012] FIGS. 16-19 illustrate in cross-sectional form another ultra-thin double gate device in accordance with another form of the present invention; and [0013] FIGS. 20 and 21 illustrate in cross-sectional form yet an ultra-thin double gate planar transistor in accordance with another form of the present invention. [0014] Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention. DETAILED DESCRIPTION [0015] Illustrated in FIG. 1 is a semiconductor device 10 in accordance with the present invention. A substrate 12 is provided. In one form substrate 12 is silicon. However, any semiconductor material may be used. An overlying dielectric layer 14 is formed. Wafer bonding or implantation of an oxygen species material may be used to form the dielectric layer 14. In one form, the dielectric layer 14 is an oxide. A semiconductor layer 16 is formed and patterned overlying a portion of the dielectric layer 14. In one form the semiconductor layer 16 is silicon and has a thickness such that an aspect ratio that is equal to the gate length divided by the thickness of semiconductor layer 16 is at least three. Therefore, semiconductor layer 16 is relatively thin. Adjacent the semiconductor layer 16 is isolation region 18. It should be understood that isolation region 18 may either be a void of material or any dielectric material. Therefore, in one form the isolation region 18 is a void. A gate dielectric 20 is formed overlying the semiconductor layer 16. A gate 22 is formed overlying the gate dielectric 20. A dielectric layer 24, such as a nitride, is formed around the gate 22 and the gate dielectric 20. The composition of dielectric layer 24 is a material that minimizes oxygen diffusion into gate dielectric 20 and is also thermally stable. Other materials in addition to nitride may therefore be used. [0016] Illustrated in FIG. 2 is further processing of semiconductor device 10. In FIG. 2 a semiconductor material 26 is selectively deposited or epitaxially grown in the source/drain regions of semiconductor device 10. In one form, the semiconductor material 26 is SiGe or even pure Ge and can be used as a material to induce stress in a transistor channel. In yet other forms semiconductor material 26 may be implemented as carbon doped silicon. If carbon doped silicon is implemented, the resulting strain as described below is tensile instead of compressive. Other semiconductor materials may also be used for semiconductor material 26. Selection of which semiconductor material will also directly affect the semiconductor device 10 threshold voltage, Vt. It should be well understood that other stressor materials may be used. In the illustrated form, the semiconductor material 26 is selectively grown. Various thicknesses may be used for semiconductor material 26. [0017] Illustrated in FIG. 3 is further processing of semiconductor device 10. In particular, a thermal process like RTA or a furnace anneal, is used to cause the semiconductor material 26 to diffuse into the underlying semiconductor layer 16. Semiconductor material 26 laterally diffuses to the source-to-channel interface and the drain-to-channel interface. The thermal processing changes the semiconductor material 26 into a diffusion source 28 of SiGe. The diffusion source 28 has a reduced concentration of Ge as a result of the diffusing from an original concentration of Ge in the as-deposited or grown layer. The SiGe diffusion source 28 has a lower Ge concentration. It should be noted that the diffusion from the diffusion source 28 is into semiconductor layer 16 and spreads toward and under the gate 22 as indicated by the arrows of FIG. 3. As a result of the Ge diffusion, the semiconductor layer 16 becomes a stressor material layer 30. A channel region underlies gate 22. The diffusion of Ge into stressor material layer 30 causes the formation of a strained channel 17. The vertical dashed line boundary of the strained channel denotes the stressor material layer 30-to-strained channel 17 boundary formed by the lateral diffusion of Ge. It should be noted that the stressor material layer 30 is immediately adjacent to the strained channel 17 and therefore can exert significant influence on the channel. [0018] In an alternative form, the diffusion of Ge into stressor material layer 30 is continued with additional thermal processing or oxidation according to the requirements of a particular semiconductor device. In one embodiment the additional processing is continued until a uniform material exists in both the stressor material layer 30 and the strained channel 17. In this form, a compressive material exists uniformly laterally in the source, the channel and the drain. The substantially uniform compressive layer that extends through the channel from the source and the drain is desirable for P-channel conductivity transistors. The remaining drawings will however illustrate a structure wherein such additional processing is not implemented and will illustrate different channel and source/drain materials. [0019] Illustrated in FIG. 4 is further processing of semiconductor device 10. In particular, extension implants are performed to create source and drain implants. The extension implants result in formation of dopants in the stressor material layer 30 and diffusion source 28. The implanted dopants into diffusion source 28 and stressor material layer 30 are annealed to form source and drain extensions in both of these layers. Continue reading... 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