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01/24/08 - USPTO Class 174 |  70 views | #20080017410 | Prev - Next | About this Page  174 rss/xml feed  monitor keywords

Method for forming a plated microvia interconnect

USPTO Application #: 20080017410
Title: Method for forming a plated microvia interconnect
Abstract: A method for forming a plated microvia interconnect. An external dielectric layer (EDL) is mounted on a substrate in direct mechanical contact with a conductive element thereon. An opening in the EDL exposes the conductive element and create a microvia in the EDL. A sidewall and bottom wall surface of the microvia are treated to promote adhesion of copper and are plated with a layer of copper that includes a copper layer on a copper seed layer and is in direct mechanical and electrical contact with the conductive element. A wet solder paste is deposited on the layer of copper to overfill a remaining portion of the microvia. The solder paste is reflowed to form a solder bump in and over the remaining portion of the microvia to form the plated microvia interconnect. A stiffener is attached to the EDL using a first adhesive. (end of abstract)



Agent: Schmeiser, Olsen & Watts - Latham, NY, US
Inventors: Miguel A. Jimarez, Ross W. Keesler, Voya R. Markovich, Rajinder S. Rai, Cheryl L. Tytran-Palomaki
USPTO Applicaton #: 20080017410 - Class: 174261000 (USPTO)

Related Patent Categories: Electricity: Conductors And Insulators, Conduits, Cables Or Conductors, Preformed Panel Circuit Arrangement (e.g., Printed Circuit), With Particular Conductive Connection (e.g., Crossover)

Method for forming a plated microvia interconnect description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20080017410, Method for forming a plated microvia interconnect.

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High-speed signal transmission structure having parallel disposed and serially connected vias
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