| Method for filling recessed micro-structures with metallization in the production of a microelectronic device -> Monitor Keywords |
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Method for filling recessed micro-structures with metallization in the production of a microelectronic deviceRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Incoherent Light Emitter Structure, EncapsulatedMethod for filling recessed micro-structures with metallization in the production of a microelectronic device description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060208272, Method for filling recessed micro-structures with metallization in the production of a microelectronic device. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of U.S. patent application Ser. No. 09/018,783, filed Feb. 4, 1998, and claims priority from U.S. patent application Ser. No. 10/882,664, filed Jul. 1, 2004, which is a continuation of U.S. patent application Ser. No. 09/815,913, filed Mar. 23, 2001, now U.S. Pat. No. 6,806,186, which is a continuation of PCT Patent Application No. PCT/US99/23189, filed Oct. 5, 1999, and which is a continuation-in-part of U.S. patent application Ser. No. 09/018,783, filed Feb. 4, 1998, and claims the benefit of U.S. Provisional Patent Application No. 60/103,061, filed Oct. 5, 1998, all of which are hereby incorporated by reference. BACKGROUND [0002] In the production of semiconductor integrated circuits and other microelectronic articles from semiconductor wafers, it is often necessary to provide multiple metal layers on a substrate to serve as interconnect metallization which electrically connects the various devices on the integrated circuit to one another. Traditionally, aluminum has been used for such interconnects, however, it is now recognized that copper metallization may be preferable. [0003] Modem semiconductor manufacturing processes, especially those used for advanced logic devices, make use of multiple layers of metal interconnects. As the length of metal interconnects increases and the cross-sectional area and spacing between them decreases, the RC delay caused by the interconnect wiring also increases. With the drive toward decreasing interconnect size and the increasing demands placed on the interconnects, the current aluminum interconnect technology becomes deficient. Copper interconnects can help alleviate many of the problems experienced in connection with the current aluminum technology. [0004] In view of the limitations of aluminum interconnect technology, the industry has sought to use copper as the interconnect metallization by using a damascene and/or patterned plating electroplating process where holes, more commonly called vias, trenches and other recesses are used to produce the desired copper patterns. In the damascene process, the wafer is first provided with a metallic seed layer and barrier/adhesion layer which are disposed over a dielectric layer into which trenches are formed. The seed layer is used to conduct electrical current during a subsequent metal electroplating step. Preferably, the seed layer is a very thin layer of metal which can be applied using one of several processes. For example, the seed layer of metal can be laid down using physical vapor deposition or chemical vapor deposition processes to produce a layer on the order of 1000 angstroms thick. The seed layer can also be formed of copper, gold, nickel, palladium, and most or all other metals. The seed layer is formed over a surface which is convoluted by the presence of the trenches, or other device features, which are recessed into the dielectric substrate. [0005] In single damascene processes using electroplating, a process employing two electroplating operations is generally employed. First, a copper layer is electroplated onto the seed layer in the form of a blanket layer. The blanket layer is plated to an extent which forms an overlying layer, with the goal of completely providing a copper layer that fills the trenches that are used to form the horizontal interconnect wiring in the dielectric substrate. The first blanket layer is then subject, for example, to a chemical mechanical polish step in which the portions of the layer extending above the trenches are removed, leaving only the trenches filled with copper. A further dielectric layer is then provided to cover the wafer surface and recessed vias are formed in the further dielectric layer. The recessed vias are disposed to overlie certain of the filled trenches. A further seed layer is applied and a further electroplated copper blanket layer is provided that extends over the surface of the further dielectric layer and fills the vias. Again, copper extending above the level of the vias is removed using, for example, chemical mechanical polishing techniques. The vias thus provide a vertical connection between the original horizontal interconnect layer and a subsequently applied horizontal interconnect layer. Electrochemical deposition of copper films has thus become an important process step in the manufacturing of high-performance microelectronic products. [0006] Alternatively, the trenches and vias may be etched in the dielectric at the same time in what is commonly called a "dual damascene" process. These features are then processed, as above, with barrier layer, seed layer and fill/blanket layer which fills the trenches and vias disposed at the bottoms of the trenches at the same time. The excess material is then polished, as above, to produce inlaid conductors. [0007] The electrical properties of the copper metallization are important to the performance of the associated microelectronic device. Such devices may fail if the copper metallization exhibits excessive electromigration that ultimately results in an open circuit condition in one or more of the metallization structures. One factor that has a very large influence on the electromigration resistance of sub-micron metal lines is the grain size of the deposited metal. This is because grain boundary migration occurs with a much lower activation energy than trans-granular migration. [0008] To achieve the desired electrical characteristics for the copper metallization, the grain structure of each deposited blanket layer is altered through an annealing process. This annealing process is traditionally thought to require the performance of a separate processing step at which the semiconductor wafer is subject to an elevated temperature of about 400 degrees Celsius. [0009] The present inventors have recognized substantial improvements over the foregoing processes employing the elevated temperature annealing. To this end, the present inventors have disclosed herein a process for filling vias, trenches, and the like using an electrochemical metal deposition process that does not require a subsequent elevated temperature annealing step or, in the alternative, that uses a subsequent elevated temperature annealing process that takes place at temperatures that are traditionally used in the copper metallization process and are compatible with low temperature semiconductor processing. SUMMARY [0010] A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a layer is deposited into the micro-structures with a process, such as an electroplating process, that generates grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature. [0011] One embodiment of the method comprises providing a semiconductor wafer with a feature that is to be connected with copper metallization. At least one dielectric layer is applied over a surface of the semiconductor wafer including the feature. Recessed micro-structures are then provided in the at least one dielectric layer. A surface of the wafer, including the recessed micro-structures, is provided with barrier/adhesion layer and a seed layer for subsequent electrochemical copper deposition. Copper metallization is electrochemically deposited on the surface of the wafer to substantially fill the recessed micro-structures. The present inventors have found that such an electrochemically deposited layer may be annealed at temperatures that are substantially lower than the temperatures typically thought necessary for such annealing. Various methods are set forth that take advantage of this finding. [0012] In a further embodiment of the disclosed method, the electrochemically deposited copper layer is allowed to self-anneal at ambient room temperature for a predetermined period of time before removing copper metallization from the surface of the wafer that extends beyond the recessed features. [0013] In accordance with a still further embodiment of the disclosed method, subsequent wafer processing, including removal of selected areas of the copper metallization, takes place without an intermediate elevated temperature annealing step and may, for example, take place before self-annealing is allowed to occur. [0014] In accordance with a still further embodiment of the method, the electrochemically deposited copper is subject to an elevated temperature annealing process. However, that annealing process takes place at a temperature below about 100 degrees Celsius or at a temperature below which an applied low-K dielectric layer suffers degradation in its mechanical and electrical properties. BRIEF DESCRIPTION OF THE DRAWINGS [0015] FIG. 1 illustrates one embodiment of a plating apparatus that may be used to apply an electrochemically deposited copper metallization layer to the surface of a semiconductor wafer in accordance with the disclosed methods. [0016] FIGS. 2A-2G illustrate the various steps used in one embodiment of the disclosed method. [0017] FIG. 3 is a graph showing the sheet resistance of an electrochemically deposited layer that has been deposited in accordance with the disclosed method as a function of time. [0018] FIGS. 4 and 5 are graphs of various x-ray scanning parameters associated with an electrochemically deposited layer that has been deposited in accordance with the disclosed method. DETAILED DESCRIPTION [0019] FIG. 1 shows various components of a processing station 10 suitable for electroplating a metal, such as copper, onto a semiconductor wafer in accordance with the disclosed method. The two principal parts of processing station 10 are a processing head, shown generally at 15, and an electroplating bowl assembly 20. It will be recognized, however, that a wide variety of processing station configurations may be used to implement the disclosed method and that the specific construction of the station 10 is merely exemplary. To this end, such a processing station may merely comprise an anode, one or more wafer contacts to render the wafer a cathode, a plating chamber having a plating bath that contacts both the wafer and the anode, and a source of plating power. Various configurations of these elements may be employed. Continue reading about Method for filling recessed micro-structures with metallization in the production of a microelectronic device... Full patent description for Method for filling recessed micro-structures with metallization in the production of a microelectronic device Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method for filling recessed micro-structures with metallization in the production of a microelectronic device patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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