| Method for fabricating transistor gate structures and gate dielectrics thereof -> Monitor Keywords |
|
|
  Method for fabricating transistor gate structures and gate dielectrics thereofUSPTO Application #: 20070072364Title: Method for fabricating transistor gate structures and gate dielectrics thereof Abstract: Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate. (end of abstract) Agent: Texas Instruments Incorporated - Dallas, TX, US Inventors: Mark R. Visokay, Luigi Colombo, James J. Chambers, Antonio L.P. Rotondaro, Haowen Bu USPTO Applicaton #: 20070072364 - Class: 438240000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Including Passive Device (e.g., Resistor, Capacitor, Etc.), Capacitor, Having High Dielectric Constant Insulator (e.g., Ta2o5, Etc.) The Patent Description & Claims data below is from USPTO Patent Application 20070072364. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is related to U.S. patent application Ser. No. 10/185,326, filed on Jun. 28, 2002, entitled ANNEAL SEQUENCE FOR HIGH-K FILM PROPERTY OPTIMIZATION; U.S. patent application Ser. No. 10/232,124, filed on Aug. 30, 2002, entitled GATE STRUCTURE AND METHOD; and U.S. Pat. No. 6,544,906, filed Oct. 25, 2001, entitled ANNEALING OF HIGH-K DIELECTRIC MATERIALS, wherein the entirety of these applications and patents are hereby incorporated by reference as if fully set forth herein. FIELD OF INVENTION [0002] The present invention relates generally to semiconductor devices and more particularly to methods for fabricating and treating high dielectric constant gate dielectrics for MOS transistor gate structures. BACKGROUND OF THE INVENTION [0003] Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET or MOS), in which a gate is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-channel and p-channel (NMOS and PMOS) transistors are used to fabricate logic and other circuitry. [0004] The source and drain are typically formed by adding dopants to targeted regions of a semiconductor body on either side of the channel. A gate structure is formed above the channel, having a gate dielectric formed over the channel and a gate electrode above the gate dielectric. The gate dielectric is an insulator material, which prevents large currents from flowing into the channel when a voltage is applied to the gate electrode, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner. Conventional MOS transistors typically include a gate dielectric formed by depositing or growing silicon dioxide (SiO.sub.2) over a silicon wafer surface, with doped polysilicon formed over the SiO.sub.2 to act as the gate electrode. [0005] Continuing trends in semiconductor device manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface. However, there are electrical and physical limitations on the extent to which thickness of SiO.sub.2 gate dielectrics can be reduced. For example, very thin SiO.sub.2 gate dielectrics are prone to large gate tunneling leakage currents resulting from direct tunneling through the thin gate oxide. In addition, there are conventional limitations on the ability to form such thin oxide films with uniform thickness. Furthermore, thin SiO.sub.2 gate dielectric layers provide a poor diffusion barrier to dopants, for example, and may allow high boron dopant penetration into the underlying channel region of the silicon during fabrication of the source/drain regions. [0006] Recent MOS transistor scaling efforts have accordingly focused on high-k dielectric materials having dielectric constants greater than that of SiO.sub.2 (e.g., greater than about 3.9), which can be formed in a thicker layer than scaled SiO.sub.2, and yet which produce equivalent field effect performance. The relative electrical performance of such high-k dielectric materials is often expressed as equivalent oxide thickness (EOT), because the high-k material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO.sub.2. Since the dielectric constant "k" is higher than that of silicon dioxide, a thicker high-k dielectric layer can be employed to mitigate tunneling leakage currents, while still achieving the equivalent electrical performance of a thinner layer of thermally grown SiO.sub.2, nitrided SiO.sub.2, or SiON. [0007] The performance and reliability of the resulting MOS transistors is dependent upon the quality of the high-k gate dielectric material, including the bulk high-k material and also the quality of the interface region between the high-k gate dielectric material and the underlying silicon. Unlike SiO.sub.2, which may be formed by thermal oxidation (growth process), high-k dielectrics are typically deposited over the semiconductor substrate, using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or other deposition processes. While the macroscopic composition (e.g., stoichiometry) of these materials may be controlled to a certain extent during such deposition processes, stoichiometric composition variations within the film may degrade device performance. [0008] In addition, the above deposition techniques often create high-k dielectric films having point defects that affect transistor performance. Such defects may include oxygen vacancies, and/or other point defects affecting leakage through the gate dielectric. Furthermore, certain deposition processes (e.g., CVD, ALD, etc.) may introduce impurities (e.g. Cl, C, OH, H, etc.) into the deposited high-k dielectric film, which also degrade device performance. Moreover, the deposited film may not be of optimal density, wherein sub par performance may result. Accordingly, there is a need for improved gate dielectric fabrication techniques by which high quality gate dielectrics and interfaces can be achieved. SUMMARY OF THE INVENTION [0009] The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. [0010] The invention provides methods for treating deposited high-k gate dielectric films and gate fabrication techniques, by which improved gate dielectric materials may be realized. A deposited dielectric film or layer is subjected to one or more non-oxidizing anneals to densify the material and one or more oxidizing anneals to mitigate material defects. In addition, the film is nitrided to inhibit dopant diffusion and to thermally stabilize the deposited material. The nitridation may be done first, or one or more of the anneals can be performed prior to nitridation to densify and/or heal defects resulting from the initial deposition process. After nitridation, one or more anneals may be performed to address any defects, impurities, etc. introduced during the nitridation, wherein the post-nitridation annealing may be performed at high temperatures without crystallization, due to the presence of nitrogen in the film. [0011] One aspect of the invention combines a post-deposition nitridation process with two or more post-deposition anneal operations, where one is oxidizing and one is non-oxidizing. In accordance with this aspect, a method is provided for treating a deposited high-k gate dielectric layer during fabrication of a semiconductor device. The method comprises nitriding a deposited high-k gate dielectric layer, performing a first anneal in a non-oxidizing ambient, and performing a second anneal in an oxidizing ambient. In one implementation, the nitridation is done prior to both the anneal processes, with the non-oxidizing anneal being done last (e.g., prior to depositing the gate electrode material). In another implementation, the non-oxidizing anneal is done prior to nitridation. Either implementation may be used in conjunction with nitrogen-containing high-k materials or with materials initially deposited with no nitrogen content, wherein the nitridation step may improve thermal stability of the deposited material in either case. [0012] Another aspect of the invention provides a post-deposition nitridation process, along with one or more pre-nitridation anneal processes and one or more post-nitridation anneal processes to treat the high-k material. In one example, the pre-nitridation anneals include a first anneal at a moderate temperature in a non-oxidizing ambient that operates to densify the deposited high-k material, wherein the temperature of the first anneal may be adjusted to avoid crystallizing the material, particularly important for deposited films initially having no nitrogen content. A second pre-nitridation anneal is then performed at moderate temperatures in an oxidizing ambient to reduce or eliminate defects and impurities in the high-k dielectric before nitridation. The post nitridation annealing in this example includes a third anneal process performed at a high temperature in a non-oxidizing ambient to densify the material, followed by a fourth anneal at a somewhat lower temperature in an oxidizing ambient to control point defects. [0013] The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. BRIEF DESCRIPTION OF THE DRAWINGS [0014] FIG. 1 is a simplified flow diagram illustrating an exemplary method of fabricating transistor gate structures in accordance with the present invention; [0015] FIG. 2 is a flow diagram illustrating another exemplary method of fabricating transistor gate structures in accordance with the invention; [0016] FIGS. 3A-3I are partial side elevation views in section illustrating a semiconductor device at various stages of fabrication processing wherein a high-k gate dielectric is formed and treated in accordance with the method of FIG. 2; and [0017] FIG. 4 is a flow diagram illustrating another exemplary method of fabricating transistor gate structures in which a deposited high-k gate dielectric material layer undergoes a high temperature non-oxidizing anneal prior to nitridation or undergoes nitridation prior to a high temperature inert non-oxidizing anneal in accordance with the invention. DETAILED DESCRIPTION OF THE INVENTION [0018] One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the devices and structures illustrated in the figures are not necessarily drawn to scale. Continue reading... Full patent description for Method for fabricating transistor gate structures and gate dielectrics thereof Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method for fabricating transistor gate structures and gate dielectrics thereof patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method for fabricating transistor gate structures and gate dielectrics thereof or other areas of interest. ### Previous Patent Application: Method for fabricating transistor gate structures and gate dielectrics thereof Next Patent Application: Method of cleaning semiconductor surfaces Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Method for fabricating transistor gate structures and gate dielectrics thereof patent info. IP-related news and info Results in 1.91618 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
||
