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Method for fabricating semiconductor devices using strained silicon bearing material

Method for fabricating semiconductor devices using strained silicon bearing material description/claims

This application claims priority to U.S. Provisional Ser. Nos. 60/523,372 filed Nov. 18, 2003 and 60/579,723 filed Jun. 14, 2004, commonly assigned, and hereby incorporated by reference for all purposes.

The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and structures for manufacturing transistor devices (e.g., MOS transistors) using strained silicon bearing materials. But it would be recognized that the invention has a much broader range of applicability.

Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.

Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process limitations exist with certain conventional processes and materials.

An example of such a process is the manufacture of such devices on conventional bulk silicon. Conventional bulk silicon has been used for numerous years. As devices become smaller, however, conventional bulk silicon has limitations. These limitations include isolation problems between transistor device structures. Additionally, conventional bulk silicon has imperfections, which lead to limitations with device speed and reliability issues. These and other limitations will be described in further detail throughout the present specification and more particularly below.

From the above, it is seen that an improved technique for processing semiconductor devices is desired

According to the present invention, techniques directed to integrated circuits and their processing for the manufacture of semiconductor devices are provided. More particularly, the invention provides a method and structures for manufacturing transistor devices (e.g., MOS transistors) using strained silicon bearing materials. But it would be recognized that the invention has a much broader range of applicability.

In a specific embodiment, the invention provides a method of manufacturing an integrated circuit on semiconductor substrates. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. The semiconductor substrate has an overlying film of material with a second lattice with a second structure and a second spacing. Preferably, the second spacing placing the film of material in either a tensile or compressive mode across the entirety of the film of material relative to the semiconductor substrate with the first structure and the first spacing. The method includes processing the film of material to form a first region and a second region within the film of material. The first region and the second region are characterized by either the tensile or compressive mode. Preferably, both the first and second regions in their entirety are characterized by either the tensile or compressive mode. The method includes processing the first region of the film of material while maintaining the second region characterized by either the tensile or the compressive mode to form an opposite characteristic from the second region. Preferably, the second region is characterized by either the compressive or the tensile mode that is kept intact and maintained. The opposite characteristic is a tensile mode if the second region is in the compressive mode and the opposite characteristic is the compressive mode if the second region is in the tensile mode.

In an alternative specific embodiment, the invention provides a method of manufacturing an integrated circuit on semiconductor substrates. The method includes providing a semiconductor substrate (e.g., silicon) characterized by a first lattice with a first structure and a first spacing. The semiconductor substrate has an overlying film of material (e.g., epitaxial silicon, germanium, silicon) with a second lattice with a second structure and a second spacing. Preferably, the second spacing places the film of material in either a tensile or compressive mode across the entirety of the film of material relative to the semiconductor substrate with the first structure and the first spacing. In a specific embodiment, the strain may be uniaxial. Here, a uniaxial strain characteristic is defined as a strain characteristic predominantly over one spatial direction over the surface of the film of material. For example, an overlying film of material made of silicon with a (100) surface orientation, a uniaxial tensile strain can be advantageously imparted along the <110> orientation to achieve significant transistor performance improvements for both NMOS and PMOS devices. Due to this <110> uniaxial stretching, a slight compressive strain will be imparted in the orthogonal <1-10> direction due to crystal deformation and related to the Poisson Ratio (v) times the tensile stress. Of course, the uniaxial strains could be tailored to specific applications by tailored different strains in the two axes, such as imparting a tensile strain in differing amounts to each of the crystal surface axes. Any combination of non-identical tensile and compressive strains along the crystal surface is defined as having a uniaxial strain characteristic. Alternatively, the strain may be biaxial having equivalent strains in the two surface axes in other embodiments. The method also includes processing a predetermined region in the film of material to cause the first tensile mode to change to a second tensile mode if the film of material is in the first tensile mode or cause the first compressive mode to change to a second compressive mode if the film of material is in the first compressive mode. Preferably, the second tensile mode provides a greater strain characteristic (e.g., absolute value, real value) in the predetermined region than the first tensile mode. The second compressive mode can provide a greater strain characteristic (e.g., absolute value, real value) in the predetermined region than the first compressive mode.

Many benefits are achieved by way of the present invention over conventional techniques. For example, the present technique provides an easy to use process that relies upon conventional technology. In some embodiments, the method may provide higher device yields in dies per wafer. Additionally, the method provides a process that is compatible with conventional process technology without substantial modifications to conventional equipment and processes. Preferably, the method provides for certain regions of silicon that are compressed other regions that are tensile and still other regions that are neither depending upon the embodiment. Depending upon the embodiment, one or more of these benefits may be achieved. These and other benefits will be described in more throughout the present specification and more particularly below.

Various additional objects, features and advantages of the present invention can be more fully appreciated with reference to the detailed description and accompanying drawings that follow.

FIGS. 1 through 3 illustrate a method for forming integrated circuits according to an embodiment of the present invention;

FIGS. 4 through 6 illustrate an alternative method for forming integrated circuits according to an embodiment of the present invention; and

FIGS. 7-14 are examples of semiconductor substrates according to embodiments of the present invention.

• Provisional Patent
• Utility Patent

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